Energy-effective issue logic

The issue logic of a dynamically-scheduled superscalar processor is a complex mechanism devoted to start the execution of multiple instructions every cycle. Due to its complexity, it is responsible for a significant percentage of the energy consumed by a microprocessor. The energy consumption of the...

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Vydáno v:Proceedings of the 28th annual international symposium on Computer architecture s. 230 - 239
Hlavní autoři: Folegnani, Daniele, González, Antonio
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 01.01.2001
Edice:ACM Conferences
Témata:
Computer systems organization > Architectures
Computer systems organization > Architectures > Distributed architectures > Grid computing
Computer systems organization > Architectures > Parallel architectures > Multicore architectures
Computer systems organization > Architectures > Serial architectures > Superscalar architectures
Computer systems organization > Dependable and fault-tolerant systems and networks
Computing methodologies > Modeling and simulation > Simulation types and techniques > Massively parallel and high-performance simulations
General and reference > Cross-computing tools and techniques > Performance
Networks > Network performance evaluation
Software and its engineering > Software organization and properties > Software system structures > Distributed systems organizing principles > Grid computing
low power
adaptive hardware
energy consumption
issue logic
ISBN:0769511627, 9780769511627
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Popis
Shrnutí:The issue logic of a dynamically-scheduled superscalar processor is a complex mechanism devoted to start the execution of multiple instructions every cycle. Due to its complexity, it is responsible for a significant percentage of the energy consumed by a microprocessor. The energy consumption of the issue logic depends on several architectural parameters, the instruction issue queue size being one of the most important. In this paper we present a technique to reduce the energy consumption of the issue logic of a high-performance superscalar processor. The proposed technique is based on the observation that the conventional issue logic wastes a significant amount of energy for useless activity. In particular, the wake-up of empty entries and operands that are ready represents an important source of energy waste. Besides, we propose a mechanism to dynamically reduce the effective size of the instruction queue. We show that on average the effective instruction queue size can be reduced by a factor of 26% with minimal impact on performance. This reduction together with the energy saved for empty and ready entries result in about 90.7% reduction in the energy consumed by the wake-up logic, which represents 14.9% of the total energy of the assumed processor.
ISBN:0769511627
9780769511627
DOI:10.1145/379240.379266