Single-tier virtual queuing: An efficacious memory controller architecture for MPSoCs with multiple realtime cores

In heterogeneous MPSoCs, memory interference between the CPU and realtime cores is a critical impediment to system performance. Previous memory schedulers adopt the classic two-tier queuing system, but unfortunately the use of two-tier queuing deteriorates the QoS of scheduling policies. In this pap...

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Veröffentlicht in:	2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) S. 1 - 6
Hauptverfasser:	Yang Song, Samadi, Kambiz, Lin, Bill
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 05.06.2016
Schlagworte:	Bandwidth Delays Graphics processing units Memory management Quality of service Random access memory Scheduling
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Zusammenfassung:	In heterogeneous MPSoCs, memory interference between the CPU and realtime cores is a critical impediment to system performance. Previous memory schedulers adopt the classic two-tier queuing system, but unfortunately the use of two-tier queuing deteriorates the QoS of scheduling policies. In this paper, we propose the Single-Tier Virtual Queuing (STVQ) memory controller for efficacious QoS-aware scheduling. The STVQ memory controller maintains single-tier transaction queues and employs separable allocation for transaction scheduling with high scalability. A multi-source realtime scheduling algorithm is further presented. The STVQ controller achieves up to 13.9% less CPU IPC slowdown than previous schedulers with no frame rate penalty on realtime cores.
DOI:	10.1145/2897937.2898093