Single-tier virtual queuing: An efficacious memory controller architecture for MPSoCs with multiple realtime cores

In heterogeneous MPSoCs, memory interference between the CPU and realtime cores is a critical impediment to system performance. Previous memory schedulers adopt the classic two-tier queuing system, but unfortunately the use of two-tier queuing deteriorates the QoS of scheduling policies. In this pap...

Full description

Saved in:
Bibliographic Details
Published in:2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors: Yang Song, Samadi, Kambiz, Lin, Bill
Format: Conference Proceeding
Language:English
Published: IEEE 05.06.2016
Subjects:
Bandwidth
Delays
Graphics processing units
Memory management
Quality of service
Random access memory
Scheduling
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Abstract In heterogeneous MPSoCs, memory interference between the CPU and realtime cores is a critical impediment to system performance. Previous memory schedulers adopt the classic two-tier queuing system, but unfortunately the use of two-tier queuing deteriorates the QoS of scheduling policies. In this paper, we propose the Single-Tier Virtual Queuing (STVQ) memory controller for efficacious QoS-aware scheduling. The STVQ memory controller maintains single-tier transaction queues and employs separable allocation for transaction scheduling with high scalability. A multi-source realtime scheduling algorithm is further presented. The STVQ controller achieves up to 13.9% less CPU IPC slowdown than previous schedulers with no frame rate penalty on realtime cores.
AbstractList In heterogeneous MPSoCs, memory interference between the CPU and realtime cores is a critical impediment to system performance. Previous memory schedulers adopt the classic two-tier queuing system, but unfortunately the use of two-tier queuing deteriorates the QoS of scheduling policies. In this paper, we propose the Single-Tier Virtual Queuing (STVQ) memory controller for efficacious QoS-aware scheduling. The STVQ memory controller maintains single-tier transaction queues and employs separable allocation for transaction scheduling with high scalability. A multi-source realtime scheduling algorithm is further presented. The STVQ controller achieves up to 13.9% less CPU IPC slowdown than previous schedulers with no frame rate penalty on realtime cores.
Author Samadi, Kambiz
Lin, Bill
Yang Song
Author_xml – sequence: 1
  surname: Yang Song
  fullname: Yang Song
  email: y6song@ucsd.edu
  organization: Electr. & Comput. Eng. Dept., Univ. of California at San Diego, La Jolla, CA, USA
– sequence: 2
  givenname: Kambiz
  surname: Samadi
  fullname: Samadi, Kambiz
  organization: Qualcomm Res., San Diego, CA, USA
– sequence: 3
  givenname: Bill
  surname: Lin
  fullname: Lin, Bill
  organization: Electr. & Comput. Eng. Dept., Univ. of California at San Diego, La Jolla, CA, USA
BookMark eNotjE9LwzAchiPowU3PHrzkC3Sm-dMk3kZRJ0wUpueRJr-4QNrMNFX27S3o6Xl44XkX6HxIAyB0U5NVXXNxR5WWmsnVTEU0O0OLmjeSKUk1uUR5F4bPCFUJkPF3yGUyEX9NMM3zPV4PGLwP1tiQphH30Kd8wjYNJacY58JkewgFbJkyYJ8yfnnbpXbEP6EccD_FEo4RcAYzWw9zmWG8QhfexBGu_7lEH48P7-2m2r4-PbfrbWWoIqVSyjrvuWGeESNNQ7RVSnvbyQaAO-oYNUYQ4cBpKblXnRBd13DnoXbMAVui27_fAAD7Yw69yae9FJxTQdgvnI5aAA
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1145/2897937.2898093
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE/IET Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 1467387290
9781467387293
EndPage 6
ExternalDocumentID 7544250
Genre orig-research
GroupedDBID 6IE
6IH
CBEJK
RIE
RIO
ID FETCH-LOGICAL-a280t-88cdff4a3f30a7a609c889fcb76ee4d2d32aa505ded9774f8b55bb64dfe1d3de3
IEDL.DBID RIE
ISICitedReferencesCount 3
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000390302500006&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Thu Jun 29 18:37:24 EDT 2023
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a280t-88cdff4a3f30a7a609c889fcb76ee4d2d32aa505ded9774f8b55bb64dfe1d3de3
PageCount 6
ParticipantIDs ieee_primary_7544250
PublicationCentury 2000
PublicationDate 2016-06-05
PublicationDateYYYYMMDD 2016-06-05
PublicationDate_xml – month: 06
  year: 2016
  text: 2016-06-05
  day: 05
PublicationDecade 2010
PublicationTitle 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)
PublicationTitleAbbrev DAC
PublicationYear 2016
Publisher IEEE
Publisher_xml – name: IEEE
Score 2.0021827
Snippet In heterogeneous MPSoCs, memory interference between the CPU and realtime cores is a critical impediment to system performance. Previous memory schedulers...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms Bandwidth
Delays
Graphics processing units
Memory management
Quality of service
Random access memory
Scheduling
Title Single-tier virtual queuing: An efficacious memory controller architecture for MPSoCs with multiple realtime cores
URI https://ieeexplore.ieee.org/document/7544250
WOSCitedRecordID wos000390302500006&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NS8NAEF1q8eBJpRW_2YNHt833brxJsXjQUqhKb2WzOwuFNpUkLfjvnUlj7cGLpywDSWCXZN7ue_OGsTuy-CaCT3iZSUSUBk5oq0liheEQMTDUPSM_XuRopKbTdNxi97taGACoxWfQo2HN5duVWdNRWZ_M2gLaoB9ImWxrtRq3Hj-K-7h1ILO3Hl6VR0TyXruUOlsMj__3nhPW_S274-NdQjllLcg7rJjgeAGiwvzFN_OC6j04_szXGH7gjzkHMoHQhrSsfEm62S_e6M8XeMc-UcARoPLX8WQ1KDmdv_IfNSEvSAU2XwInU8uyy96HT2-DZ9E0ShA6UF4llDLWuUiHLvS01ImXGqVSZzKZAEQ2sGGgNUIdC5bgnlNZHGdZElkHvg0thGesna9yOGfch9Q3JvOUA_ycAVLpW3y8k4F1RPFdsA7N1-xz64Uxa6bq8u_wFTtCgJHU0qr4mrWrYg037NBsqnlZ3NYL-A0YlKHZ
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NS8NAEF1KFfSk0orfzsGj2-Y7G29SLBXbUmiV3spmdxYKbSppWvDfuxOj9uDFU5aBJLBLMm_3vXnD2B1ZfBPBx51URTxIPMOlliSxsmHfYmAse0a-9ePhUEynyajG7n9qYRCxFJ9hi4Yll69XakNHZW0ya_Nog75HnbOqaq3Kr8cNwrbdPJDdW8tehUNU8k7DlDJfdI_-96Zj1vwtvIPRT0o5YTXMGiwf2_ECeWEzGGznOVV8gP2db2z4AR4zQLKBkIrUrLAk5ewHVAr0hb1jlyoAC1FhMBqvOmugE1j41hNCTjqw-RKBbC3XTfbafZp0erxqlcClJ5yCC6G0MYH0je_IWEZOooRIjErjCDHQnvY9KS3Y0agJ8BmRhmGaRoE26Gpfo3_K6tkqwzMGLiauUqkjDNoPGjGJXW0fb2JPGyL5zlmD5mv2_uWGMaum6uLv8C076E0G_Vn_efhyyQ4t3IhKoVV4xepFvsFrtq-2xXyd35SL-Qmt7KUi
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2016+53nd+ACM%2FEDAC%2FIEEE+Design+Automation+Conference+%28DAC%29&rft.atitle=Single-tier+virtual+queuing%3A+An+efficacious+memory+controller+architecture+for+MPSoCs+with+multiple+realtime+cores&rft.au=Yang+Song&rft.au=Samadi%2C+Kambiz&rft.au=Lin%2C+Bill&rft.date=2016-06-05&rft.pub=IEEE&rft.spage=1&rft.epage=6&rft_id=info:doi/10.1145%2F2897937.2898093&rft.externalDocID=7544250