Advanced technology mapping for standard-cell generators

In this paper, a new algorithm for technology mapping aiming standard-cell generators is proposed. The proposed method has features that explore several AND/OR circuit decompositions by using a n-ary tree representation of the circuit. In the covering step, the cell that leads to the smaller depth i...

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Veröffentlicht in:Proceedings of the 17th symposium on Integrated circuits and system design S. 254 - 259
Hauptverfasser: Correia, Vinícius, Reis, André
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: New York, NY, USA ACM 04.09.2004
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Algorithm design and analysis
Area measurement
Circuit simulation
Circuit synthesis
Gain measurement
Hardware
Hardware > Integrated circuits > Logic circuits
Libraries
Logic design
Permission
Timing
cell library
complex gates
logic synthesis
technology mapping
library-free
ISBN:1581139470, 9781581139471
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:In this paper, a new algorithm for technology mapping aiming standard-cell generators is proposed. The proposed method has features that explore several AND/OR circuit decompositions by using a n-ary tree representation of the circuit. In the covering step, the cell that leads to the smaller depth increase is chosen. Depth calculation is not limited to the subject tree and takes into account all previously mapped trees representing sub-expressions used as inputs. Experimental results show gains in circuit depth measured by the number of gates in series, as well as in area measured by transistor count when compared to SIS mapping approach using the same libraries. The gain in circuit depth translates to better timing as verified by spice simulations.
Bibliographie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:1581139470
9781581139471
DOI:10.1145/1016568.1016636