A robust edge encoding technique for energy-efficient multi-cycle interconnect

In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy...

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Bibliographic Details
Published in:ISLPED '07 : proceedings of the International Symposium on Low Power Electronics and Design : Portland, Oregon, USA, August 27-29, 2007 pp. 68 - 73
Main Authors: Jae-sun Seo, Sylvester, D, Blaauw, D, Kaul, H, Krishnamurthy, R
Format: Conference Proceeding
Language:English
Published: IEEE 01.08.2007
Subjects:
Algorithm design and analysis
Circuits
Clustering algorithms
CMOS technology
Delay estimation
Encoding
Energy efficiency
interconnect
multi-cycle interconnect
repeaters
Robustness
Timing
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Summary:In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 38% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be more robust to process variations than previous techniques.
DOI:10.1145/1283780.1283796