A robust edge encoding technique for energy-efficient multi-cycle interconnect - Jae-sun Seo; Sylvester, D; Blaauw, D; Kaul, H; Krishnamurthy, R (ISLPED '07 : proceedings of the International Symposium on Low Power Electronics and Design : Portland, Oregon, USA, August 27-29, 2007, 2007)
In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 38% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be more robust to process variations than previous techniques.