A robust edge encoding technique for energy-efficient multi-cycle interconnect

In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy...

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Vydáno v:ISLPED '07 : proceedings of the International Symposium on Low Power Electronics and Design : Portland, Oregon, USA, August 27-29, 2007 s. 68 - 73
Hlavní autoři: Jae-sun Seo, Sylvester, D, Blaauw, D, Kaul, H, Krishnamurthy, R
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.08.2007
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Abstract In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 38% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be more robust to process variations than previous techniques.
AbstractList In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 38% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be more robust to process variations than previous techniques.
Author Blaauw, D
Sylvester, D
Kaul, H
Krishnamurthy, R
Jae-sun Seo
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  surname: Jae-sun Seo
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  givenname: D
  surname: Sylvester
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  email: dmcs@unnich.edu
  organization: Dept. of EECS, Univ. of Michigan, Ann Arbor, MI, USA
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  givenname: D
  surname: Blaauw
  fullname: Blaauw, D
  email: blaauw@unnich.edu
  organization: Dept. of EECS, Univ. of Michigan, Ann Arbor, MI, USA
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  givenname: H
  surname: Kaul
  fullname: Kaul, H
  email: himanshu.kaul@intel.com
  organization: Circuit Res. Lab., Intel Corp., Hillsboro, OR, USA
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  givenname: R
  surname: Krishnamurthy
  fullname: Krishnamurthy, R
  email: ram.khshnannurthy@intel.com
  organization: Circuit Res. Lab., Intel Corp., Hillsboro, OR, USA
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Snippet In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are...
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StartPage 68
SubjectTerms Algorithm design and analysis
Circuits
Clustering algorithms
CMOS technology
Delay estimation
Encoding
Energy efficiency
interconnect
multi-cycle interconnect
repeaters
Robustness
Timing
Title A robust edge encoding technique for energy-efficient multi-cycle interconnect
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