Optimizing Persistent Memory Transactions

Byte-addressable, non-volatile, random access memory (NVM) has the potential to dramatically accelerate the performance of storage-intensive workloads. For applications with irregular data access patterns, and applications that rely on ad-hoc data structures, the most promising model for interacting...

Full description

Saved in:
Bibliographic Details
Published in:Proceedings / International Conference on Parallel Architectures and Compilation Techniques pp. 219 - 231
Main Authors: Zardoshti, Pantea, Zhou, Tingzhe, Liu, Yujie, Spear, Michael
Format: Conference Proceeding
Language:English
Published: IEEE 01.09.2019
Subjects:
Concurrency
Hardware
Non volatile Memory
Nonvolatile memory
Optimization
Persistence
Programming
Random access memory
Scalability
Synchronization
Throughput
Transactional Memory
ISSN:2641-7936
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Abstract Byte-addressable, non-volatile, random access memory (NVM) has the potential to dramatically accelerate the performance of storage-intensive workloads. For applications with irregular data access patterns, and applications that rely on ad-hoc data structures, the most promising model for interacting with NVM is a transactional model. However, the specifics of the model matter significantly. We introduce two models for programming persistent transactions. We show how to build concurrent persistent transactional memory from traditional software transactional memories. We then introduce general and model-specific optimizations that can substantially improve the performance of persistent transactions. Our evaluation shows a substantial improvement in the both the latency and scalability of persistent transactions.
AbstractList Byte-addressable, non-volatile, random access memory (NVM) has the potential to dramatically accelerate the performance of storage-intensive workloads. For applications with irregular data access patterns, and applications that rely on ad-hoc data structures, the most promising model for interacting with NVM is a transactional model. However, the specifics of the model matter significantly. We introduce two models for programming persistent transactions. We show how to build concurrent persistent transactional memory from traditional software transactional memories. We then introduce general and model-specific optimizations that can substantially improve the performance of persistent transactions. Our evaluation shows a substantial improvement in the both the latency and scalability of persistent transactions.
Author Zardoshti, Pantea
Zhou, Tingzhe
Liu, Yujie
Spear, Michael
Author_xml – sequence: 1
  givenname: Pantea
  surname: Zardoshti
  fullname: Zardoshti, Pantea
  organization: Lehigh University
– sequence: 2
  givenname: Tingzhe
  surname: Zhou
  fullname: Zhou, Tingzhe
  organization: Facebook
– sequence: 3
  givenname: Yujie
  surname: Liu
  fullname: Liu, Yujie
  organization: Google
– sequence: 4
  givenname: Michael
  surname: Spear
  fullname: Spear, Michael
  organization: Lehigh University
BookMark eNotjj1PwzAUAA0CiaYwM7BkZUjq55cX22MV8SW1aocgsVVO9IyMiFPFWcqvpxJMN5x0ukxcxTGyEPcgSwBpV_t105ZKgi2llIouRAZaGcAa8ONSLFRdQaEt1jciS-lLygpqwoV43B3nMISfED_zPU8ppJnjnG95GKdT3k4uJtfPYYzpVlx795347p9L8f781DavxWb38tasN4VTmuaiJ7LKOuy0tlxplJ6cqTQhoXLedliTMXw2pDqviQgUA3W95073smdcioe_bmDmw3EKg5tOB2PseVjhL1rrQgU
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/PACT.2019.00025
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Xplore POP ALL
IEEE Xplore All Conference Proceedings
IEEE/IET Electronic Library (IEL) (UW System Shared)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE/IET Electronic Library (IEL) (UW System Shared)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Computer Science
EISBN 172813613X
9781728136134
EISSN 2641-7936
EndPage 231
ExternalDocumentID 8891652
Genre orig-research
GroupedDBID 123
23M
29O
6IE
6IL
ACGFS
AFFNX
ALMA_UNASSIGNED_HOLDINGS
CBEJK
M43
RIE
RIL
RNS
ID FETCH-LOGICAL-a275t-c55929a3b779e4730f5a84753532af9b36588ee4752bf755512e15bcfeb7c0ce3
IEDL.DBID RIE
ISICitedReferencesCount 9
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000550990200017&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Aug 27 02:43:19 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a275t-c55929a3b779e4730f5a84753532af9b36588ee4752bf755512e15bcfeb7c0ce3
PageCount 13
ParticipantIDs ieee_primary_8891652
PublicationCentury 2000
PublicationDate 2019-Sept.
PublicationDateYYYYMMDD 2019-09-01
PublicationDate_xml – month: 09
  year: 2019
  text: 2019-Sept.
PublicationDecade 2010
PublicationTitle Proceedings / International Conference on Parallel Architectures and Compilation Techniques
PublicationTitleAbbrev PACT
PublicationYear 2019
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0041653
ssib057737306
Score 2.1439936
Snippet Byte-addressable, non-volatile, random access memory (NVM) has the potential to dramatically accelerate the performance of storage-intensive workloads. For...
SourceID ieee
SourceType Publisher
StartPage 219
SubjectTerms Concurrency
Hardware
Non volatile Memory
Nonvolatile memory
Optimization
Persistence
Programming
Random access memory
Scalability
Synchronization
Throughput
Transactional Memory
Title Optimizing Persistent Memory Transactions
URI https://ieeexplore.ieee.org/document/8891652
WOSCitedRecordID wos000550990200017&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV09T8MwELVKxcBUoEV8KwMLEqGJHffsEVVULJQORepW2c5Z6kCK2rQS_HrOadoysLBFTizlcvbdU_zuHmN32quM5xUPh9yQ5RpoS9k8dsYp6VH5DPNKbAKGQzWZ6FGDPexqYRCxIp_hY7iszvLzuVuFX2VdpQjMSAq4BwCwqdXarh0JIGix9rZRmHCGFHUrnzTR3dFTfxyIXKE7ZRJ0sX9pqVSpZND630scs86-Ji8a7bLNCWtgccpaW1GGqN6jbXb_RkHgY_ZND0WB3h7cWJTRa2DUfkXjvTz4ssPeB8_j_ktc6yHEhoMsY0fon2sjLIDGjKz10lBykUIKbry2gtCEQrojufUgCQtxTKV1Hi24xKE4Y81iXuA5izILmcGeoukukya1PuU8sb3cazDe4wVrB8unn5uWF9Pa6Mu_h6_YUfi0G-rVNWuWixXesEO3LmfLxW3lpx8FUpNg
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PT8IwFH4haKInVDD-dgcvJk62rqXt0RgJRkAOM-FG2u414eAwMEz0r7cdAzx48bZ0a7K31773Zf3e-wBupBWUZCUPx7mBZpK7LaWz0CgjmEVhKWal2AQfDsV4LEc1uNvUwiBiST7De39ZnuVnM7P0v8raQjgww1zA3WGUknhVrbVePYzzxC3XzjoOO6TBkqqZTxzJ9ujhMfVULt-fMvLK2L_UVMpk0m387zUOoLWtygtGm3xzCDXMj6CxlmUIql3ahNtXFwbep9_uocAT3L0j8yIYeE7tV5BuBcIXLXjrPqWPvbBSRAgV4awIjcP_RKpEcy6ROmstUy69sIQlRFmpE4cnBLo7jGjLmUNDBGOmjUXNTWQwOYZ6PsvxBAKqOVXYEW66oUzF2saERLqTWcmVtXgKTW_55GPV9GJSGX329_A17PXSQX_Sfx6-nMO-_8wrItYF1Iv5Ei9h13wW08X8qvTZD-K9lqc
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=proceeding&rft.title=Proceedings+%2F+International+Conference+on+Parallel+Architectures+and+Compilation+Techniques&rft.atitle=Optimizing+Persistent+Memory+Transactions&rft.au=Zardoshti%2C+Pantea&rft.au=Zhou%2C+Tingzhe&rft.au=Liu%2C+Yujie&rft.au=Spear%2C+Michael&rft.date=2019-09-01&rft.pub=IEEE&rft.eissn=2641-7936&rft.spage=219&rft.epage=231&rft_id=info:doi/10.1109%2FPACT.2019.00025&rft.externalDocID=8891652