On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections betwee...

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Bibliographic Details
Published in:	Design, Automation and Test in Europe pp. 1290 - 1295
Main Authors:	Kastensmidt, F. Lima, Sterpone, L., Carro, L., Reorda, M. Sonza
Format:	Conference Proceeding
Language:	English
Published:	Washington, DC, USA IEEE Computer Society 07.03.2005 IEEE
Series:	ACM Conferences
Subjects:	Circuit faults Computer systems organization > Architectures > Other architectures > Reconfigurable computing Computer systems organization > Architectures > Other architectures > Self-organizing autonomic computing Fault tolerance Field programmable gate arrays Hardware > Hardware test Hardware > Integrated circuits > Semiconductor memory > Static memory Hardware > Robustness Hardware > Very large scale integration design > Application-specific VLSI designs Logic design Protection Redundancy Robustness Routing Signal design Signal generators
ISBN:	9780769522883, 0769522882
ISSN:	1530-1591
Online Access:	Get full text
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