A Novel Unified Architecture for Public-Key Cryptography

In this paper we propose a fully-parallel, bit-sliced unified architecture designed to perform modular multipication/exponentiation and GF(2^M) multiplication as the core operations of RSA and EC cryptography. The architecture uses radix-2 Montgomery technique for modular arithmetic, and a radix-4 M...

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Vydáno v:Design, Automation and Test in Europe s. 52 - 57
Hlavní autoři: Cilardo, A., Mazzeo, A., Mazzocca, N., Romano, L.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: Washington, DC, USA IEEE Computer Society 07.03.2005
IEEE
Edice:ACM Conferences
Témata:
Arithmetic
Clocks
Computer architecture
Computer systems organization > Architectures > Other architectures > Reconfigurable computing
Computer systems organization > Architectures > Other architectures > Self-organizing autonomic computing
Computing methodologies > Symbolic and algebraic manipulation > Symbolic and algebraic algorithms > Algebraic algorithms
Costs
Elliptic curve cryptography
Field programmable gate arrays
Hardware
Hardware > Very large scale integration design > Application-specific VLSI designs
Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific processors
Proposals
Public key
Public key cryptography
Security and privacy > Cryptography > Public key (asymmetric) techniques
Security and privacy > Cryptography > Public key (asymmetric) techniques > Public key encryption
ISBN:9780769522883, 0769522882
ISSN:1530-1591
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Popis
Shrnutí:In this paper we propose a fully-parallel, bit-sliced unified architecture designed to perform modular multipication/exponentiation and GF(2^M) multiplication as the core operations of RSA and EC cryptography. The architecture uses radix-2 Montgomery technique for modular arithmetic, and a radix-4 MSD-first approach for GF(2^M) multiplication. To the best of our knowledge, it is the first unified proposal based on such a hybrid approach. The architecture structure is bit-sliced and is highly regular, modular, and scalable, as virtually any datapath length can be obtained at a linear cost in terms of hardware resources and no costs in terms of critical path. Our proposal outperforms all similar unified architectures found in the technical literature in terms of clock count and critical path. The architecture has been implemented on a Field-Programmable Gate Array (FPGA) device. A highly compact and efficient design was obtained taking advantage of the architectural characteristics.
Bibliografie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780769522883
0769522882
ISSN:1530-1591
DOI:10.1109/DATE.2005.28