A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow that generates and configures application-specifi...

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Bibliographic Details
Published in:	Design, Automation and Test in Europe pp. 1182 - 1187
Main Authors:	Goossens, Kees, Dielissen, John, Gangwal, Om Prakash, Pestana, Santiago Gonzalez, Radulescu, Andrei, Rijpkema, Edwin
Format:	Conference Proceeding
Language:	English
Published:	Washington, DC, USA IEEE Computer Society 07.03.2005 IEEE
Series:	ACM Conferences
Subjects:	Acceleration Analytical models Application software Hardware Hardware > Hardware validation Hardware > Integrated circuits > Interconnect Intellectual property Network-on-a-chip Networks > Network protocols Performance analysis Social and professional topics > Professional topics > Management of computing and information systems > Project and people management > Systems analysis and design Software performance Software tools System-on-a-chip
ISBN:	9780769522883, 0769522882
ISSN:	1530-1591
Online Access:	Get full text
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