A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow that generates and configures application-specifi...
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| Veröffentlicht in: | Design, Automation and Test in Europe S. 1182 - 1187 |
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| Format: | Tagungsbericht |
| Sprache: | Englisch |
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Washington, DC, USA
IEEE Computer Society
07.03.2005
IEEE |
| Schriftenreihe: | ACM Conferences |
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| ISBN: | 9780769522883, 0769522882 |
| ISSN: | 1530-1591 |
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| Abstract | Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow that generates and configures application-specific network on chip (NOC) instances, given application communication requirements. The NOC can be simulated in SystemC and RTL VHDL. An independent performance verification tool verifies analytically that the NOC instance (hardware) and its configuration (software) together meet the application performance requirements. The Æthereal NOC's guaranteed performance is essential to replace time-consuming simulation by fast analytical performance validation. As a result, application-specific NOCs that are guaranteed to meet the application's communication requirements are generated and verified in minutes, reducing the number of design iterations. A realistic MPEG SOC example substantiates our claims. |
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| AbstractList | Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow that generates and configures application-specific network on chip (NOC) instances, given application communication requirements. The NOC can be simulated in SystemC and RTL VHDL. An independent performance verification tool verifies analytically that the NOC instance (hardware) and its configuration (software) together meet the application performance requirements. The Æthereal NOC's guaranteed performance is essential to replace time-consuming simulation by fast analytical performance validation. As a result, application-specific NOCs that are guaranteed to meet the application's communication requirements are generated and verified in minutes, reducing the number of design iterations. A realistic MPEG SOC example substantiates our claims. Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow that generates and configures application-specific network on chip (NOC) instances, given application communication requirements. The NOC can be simulated in SystemC and RTL VHDL. An independent performance verification tool verifies analytically that the NOC instance (hardware) and its configuration (software) together meet the application performance requirements. The Aethereal NOC's guaranteed performance is essential to replace time-consuming simulation by fast analytical performance validation. As a result, application-specific NOCs that are guaranteed to meet the application's communication requirements are generated and verified in minutes, reducing the number of design iterations. A realistic MPEG SOC example substantiates our claims. |
| Author | Rijpkema, Edwin Goossens, Kees Gangwal, Om Prakash Radulescu, Andrei Pestana, Santiago Gonzalez Dielissen, John |
| Author_xml | – sequence: 1 givenname: Kees surname: Goossens fullname: Goossens, Kees organization: Philips Research Laboratories, Eindhoven, The Netherlands – sequence: 2 givenname: John surname: Dielissen fullname: Dielissen, John organization: Philips Research Laboratories, Eindhoven, The Netherlands – sequence: 3 givenname: Om Prakash surname: Gangwal fullname: Gangwal, Om Prakash organization: Philips Research Laboratories, Eindhoven, The Netherlands – sequence: 4 givenname: Santiago Gonzalez surname: Pestana fullname: Pestana, Santiago Gonzalez organization: Philips Research Laboratories, Eindhoven, The Netherlands – sequence: 5 givenname: Andrei surname: Radulescu fullname: Radulescu, Andrei organization: Philips Research Laboratories, Eindhoven, The Netherlands – sequence: 6 givenname: Edwin surname: Rijpkema fullname: Rijpkema, Edwin organization: Philips Research Laboratories, Eindhoven, The Netherlands |
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| SubjectTerms | Acceleration Analytical models Application software Hardware Hardware -- Hardware validation Hardware -- Integrated circuits -- Interconnect Intellectual property Network-on-a-chip Networks -- Network protocols Performance analysis Social and professional topics -- Professional topics -- Management of computing and information systems -- Project and people management -- Systems analysis and design Software performance Software tools System-on-a-chip |
| Title | A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification |
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