Goossens, K., Dielissen, J., Gangwal, O. P., Pestana, S. G., Radulescu, A., & Rijpkema, E. (2005, March 7). A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. Design, Automation and Test in Europe, 1182-1187. https://doi.org/10.1109/DATE.2005.11
Citace podle Chicago (17th ed.)Goossens, Kees, John Dielissen, Om Prakash Gangwal, Santiago Gonzalez Pestana, Andrei Radulescu, a Edwin Rijpkema. "A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification." Design, Automation and Test in Europe 7 Mar. 2005: 1182-1187. https://doi.org/10.1109/DATE.2005.11.
Citace podle MLA (9th ed.)Goossens, Kees, et al. "A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification." Design, Automation and Test in Europe, 7 Mar. 2005, pp. 1182-1187, https://doi.org/10.1109/DATE.2005.11.