Architectural synthesis of performance-driven multipliers with accumulator interleaving

VLSI multipliers assume different characteristics in terms of latency, throughput and area for different target applications. This paper proposes a methodology of automatically generating a multiplier from the user's specifications of latency, throughput, and area. The entire gamut of multiplie...

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Veröffentlicht in:	30th ACM/IEEE Design Automation Conference S. 303 - 307
Hauptverfasser:	Ghosh, Debabrata, Nandy, S. K., Sadayappan, P., Parthasarathy, K.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	New York, NY, USA ACM 01.07.1993
Schriftenreihe:	ACM Conferences
Schlagworte:	Database machines Delay Design methodology Hardware > Electronic design automation > High-level and register-transfer level synthesis Hardware > Electronic design automation > High-level and register-transfer level synthesis > Datapath optimization Hardware > Electronic design automation > Logic synthesis > Circuit optimization Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits Hardware > Very large scale integration design Hardware > Very large scale integration design > VLSI packaging > Input > output styles Instruments Interleaved codes Logic Pipeline processing Space technology Throughput Very large scale integration
ISBN:	9780897915779, 0897915771
ISSN:	0738-100X
Online-Zugang:	Volltext
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