Architectural synthesis of performance-driven multipliers with accumulator interleaving - Ghosh, Debabrata; Nandy, S. K.; Sadayappan, P.; Parthasarathy, K. (30th ACM/IEEE Design Automation Conference, 1993)
VLSI multipliers assume different characteristics in terms of latency, throughput and area for different target applications. This paper proposes a methodology of automatically generating a multiplier from the user's specifications of latency, throughput, and area. The entire gamut of multipliers, starting from low area, moderate performance multipliers to high performance ones with low latency and/or very high throughput is captured in this synthesis procedure. The architecture comprises of a smaller core, a Front End Server (FES) and a Back End Processor (BEP) which allows to use the basic core repetitively for multiplication of larger numbers. Through a novel method of accumulator interleaving the multipliers designed using the proposed methodology support better performance compared to conventional approaches. The proposed methodology can be used for synthesis of multipliers occupying any place (feasible in a given technology) in the A - L - T (Area, Latency, Throughput) space, subject to an affordable power dissipation.