Ghosh, D., Nandy, S. K., Sadayappan, P., & Parthasarathy, K. (1993, July). Architectural synthesis of performance-driven multipliers with accumulator interleaving. 30th ACM/IEEE Design Automation Conference, 303-307. https://doi.org/10.1145/157485.164902
Chicago-Zitierstil (17. Ausg.)Ghosh, Debabrata, S. K. Nandy, P. Sadayappan, und K. Parthasarathy. "Architectural Synthesis of Performance-driven Multipliers with Accumulator Interleaving." 30th ACM/IEEE Design Automation Conference Jul. 1993: 303-307. https://doi.org/10.1145/157485.164902.
MLA-Zitierstil (9. Ausg.)Ghosh, Debabrata, et al. "Architectural Synthesis of Performance-driven Multipliers with Accumulator Interleaving." 30th ACM/IEEE Design Automation Conference, Jul. 1993, pp. 303-307, https://doi.org/10.1145/157485.164902.