Dynamic Verification of Sequential Consistency

In this paper, we develop the first feasibly implementable scheme for end-to-end dynamic verification of multithreaded memory systems. For multithreaded (including multiprocessor) memory systems, end-to-end correctness is defined by its memory consistency model. One such consistency model is sequent...

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Veröffentlicht in:32nd International Symposium on Computer Architecture (ISCA'05) S. 482 - 493
Hauptverfasser: Meixner, Albert, Sorin, Daniel J.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: Washington, DC, USA IEEE Computer Society 01.05.2005
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Bandwidth
Bit error rate
Coherence
Computer architecture
Computer science
Computer systems organization > Architectures > Parallel architectures > Multiple instruction, multiple data
Control systems
General and reference > Cross-computing tools and techniques > Design
Hardware
Hardware > Electronic design automation > High-level and register-transfer level synthesis
Hardware > Hardware validation > Functional verification
Hardware > Integrated circuits
Hardware > Integrated circuits > Logic circuits > Sequential circuits
Hardware > Integrated circuits > Semiconductor memory
Multiprocessor interconnection networks
Protocols
System recovery
ISBN:076952270X, 9780769522708
ISSN:1063-6897
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:In this paper, we develop the first feasibly implementable scheme for end-to-end dynamic verification of multithreaded memory systems. For multithreaded (including multiprocessor) memory systems, end-to-end correctness is defined by its memory consistency model. One such consistency model is sequential consistency (SC), which specifies that all loads and stores appear to execute in a total order that respects program order for each thread. Our design, DVSC-Indirect, performs dynamic verification of SC (DVSC) by dynamically verifying a set of sub-invariants that, when taken together, have been proven equivalent to SC. We evaluate DVSC-Indirect with full-system simulation and commercial workloads. Our results for multiprocessor systems with both directory and snooping cache coherence show that DVSC-Indirect detects all injected errors that affect system correctness (i.e., SC). We show that it uses only a small amount more bandwidth (less than 25%) than an unprotected system and thus can achieve comparable performance when provided with only modest additional link bandwidth.
Bibliographie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:076952270X
9780769522708
ISSN:1063-6897
DOI:10.1109/ISCA.2005.25