Dynamic Verification of Sequential Consistency

In this paper, we develop the first feasibly implementable scheme for end-to-end dynamic verification of multithreaded memory systems. For multithreaded (including multiprocessor) memory systems, end-to-end correctness is defined by its memory consistency model. One such consistency model is sequent...

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Vydané v:	32nd International Symposium on Computer Architecture (ISCA'05) s. 482 - 493
Hlavní autori:	Meixner, Albert, Sorin, Daniel J.
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	Washington, DC, USA IEEE Computer Society 01.05.2005 IEEE
Edícia:	ACM Conferences
Predmet:	Bandwidth Bit error rate Coherence Computer architecture Computer science Computer systems organization > Architectures > Parallel architectures > Multiple instruction, multiple data Control systems General and reference > Cross-computing tools and techniques > Design Hardware Hardware > Electronic design automation > High-level and register-transfer level synthesis Hardware > Hardware validation > Functional verification Hardware > Integrated circuits Hardware > Integrated circuits > Logic circuits > Sequential circuits Hardware > Integrated circuits > Semiconductor memory Multiprocessor interconnection networks Protocols System recovery
ISBN:	076952270X, 9780769522708
ISSN:	1063-6897
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