Dynamic Verification of Sequential Consistency
In this paper, we develop the first feasibly implementable scheme for end-to-end dynamic verification of multithreaded memory systems. For multithreaded (including multiprocessor) memory systems, end-to-end correctness is defined by its memory consistency model. One such consistency model is sequent...
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| Published in: | 32nd International Symposium on Computer Architecture (ISCA'05) pp. 482 - 493 |
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| Main Authors: | , |
| Format: | Conference Proceeding |
| Language: | English |
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Washington, DC, USA
IEEE Computer Society
01.05.2005
IEEE |
| Series: | ACM Conferences |
| Subjects: | |
| ISBN: | 076952270X, 9780769522708 |
| ISSN: | 1063-6897 |
| Online Access: | Get full text |
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| Abstract | In this paper, we develop the first feasibly implementable scheme for end-to-end dynamic verification of multithreaded memory systems. For multithreaded (including multiprocessor) memory systems, end-to-end correctness is defined by its memory consistency model. One such consistency model is sequential consistency (SC), which specifies that all loads and stores appear to execute in a total order that respects program order for each thread. Our design, DVSC-Indirect, performs dynamic verification of SC (DVSC) by dynamically verifying a set of sub-invariants that, when taken together, have been proven equivalent to SC. We evaluate DVSC-Indirect with full-system simulation and commercial workloads. Our results for multiprocessor systems with both directory and snooping cache coherence show that DVSC-Indirect detects all injected errors that affect system correctness (i.e., SC). We show that it uses only a small amount more bandwidth (less than 25%) than an unprotected system and thus can achieve comparable performance when provided with only modest additional link bandwidth. |
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| AbstractList | In this paper, we develop the first feasibly implementable scheme for end-to-end dynamic verification of multithreaded memory systems. For multithreaded (including multiprocessor) memory systems, end-to-end correctness is defined by its memory consistency model. One such consistency model is sequential consistency (SC), which specifies that all loads and stores appear to execute in a total order that respects program order for each thread. Our design, DVSC-Indirect, performs dynamic verification of SC (DVSC) by dynamically verifying a set of sub-invariants that, when taken together, have been proven equivalent to SC. We evaluate DVSC-Indirect with full-system simulation and commercial workloads. Our results for multiprocessor systems with both directory and snooping cache coherence show that DVSC-Indirect detects all injected errors that affect system correctness (i.e., SC). We show that it uses only a small amount more bandwidth (less than 25%) than an unprotected system and thus can achieve comparable performance when provided with only modest additional link bandwidth. In this paper, we develop the first feasibly implemental scheme for end-to-end dynamic verification of multithreaded memory systems. For multithreaded (including multiprocessor) memory systems, end-to-end correctness is defined by its memory consistency model. One such consistency model is sequential consistency (SC), which specifies that all loads and stores appear to execute in a total order that respects program order for each thread. Our design, DVSC-Indirect, performs dynamic verification of SC (DVSC) by dynamically verifying a set of sub-invariants that, when taken together, have been proven equivalent to SC. We evaluate DVSC-Indirect with full-system simulation and commercial workloads. Our results for multiprocessor systems with both directory and snooping cache coherence show that DVSC-Indirect detects all injected errors that affect system correctness (i.e., SC). We show that it uses only a small amount more bandwidth (less than 25%) than an unprotected system and thus can achieve comparable performance when provided with only modest additional link bandwidth. |
| Author | Meixner, Albert Sorin, Daniel J. |
| Author_xml | – sequence: 1 givenname: Albert surname: Meixner fullname: Meixner, Albert organization: Duke University – sequence: 2 givenname: Daniel J. surname: Sorin fullname: Sorin, Daniel J. organization: Duke University |
| BookMark | eNqNkD1PwzAURS1RJNrSjY0lCywo4T07TuKxCl-VKjEUEJvluC-SIYlLnA7996QqP4C7vOEePV2dGZt0viPGrhASRFD3q025TDiATLg8YzPIMyU5z-FzwqYImYizQuUXbBHCF4xJJXLkU5Y8HDrTOht9UO9qZ83gfBf5OtrQz566wZkmKn0XXBios4dLdl6bJtDi787Z-9PjW_kSr1-fV-VyHRue8yGWaATIlIraKJUKRRnZjEsCawzw3FYI24KgtkrISkqhMLcGATNh0G55Jubs9vR31_txRxh064KlpjEd-X3QAjFPpRAjeH0CHRHpXe9a0x80pgJlAWN7d2qNbXXl_XfQCProSx996aMvzaWuekf1SN_8hxa_GkZpHw |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO 7SC 8FD JQ2 L7M L~C L~D |
| DOI | 10.1109/ISCA.2005.25 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEL IEEE Proceedings Order Plans (POP) 1998-present Computer and Information Systems Abstracts Technology Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional |
| DatabaseTitle | Computer and Information Systems Abstracts Technology Research Database Computer and Information Systems Abstracts – Academic Advanced Technologies Database with Aerospace ProQuest Computer Science Collection Computer and Information Systems Abstracts Professional |
| DatabaseTitleList | Computer and Information Systems Abstracts |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE/IET Electronic Library url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Computer Science |
| EndPage | 493 |
| ExternalDocumentID | 1431580 |
| Genre | orig-research Conference Paper |
| GroupedDBID | 6IE 6IF 6IG 6IH 6IK 6IL 6IM 6IN AAJGR AARBI ACM ADPZR ALMA_UNASSIGNED_HOLDINGS APO BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK GUFHI IERZE OCL RIB RIC RIE RIL RIO 23M 29F 29O AAWTH ACGFS ADZIZ CHZPO IEGSK IJVOP IPLJI M43 ZY4 7SC 8FD JQ2 L7M L~C L~D |
| ID | FETCH-LOGICAL-a272t-51a3054e8fa99439e6ec625e0caa027cb10d8e0fc935b553917ca10163a1cd263 |
| IEDL.DBID | RIE |
| ISBN | 076952270X 9780769522708 |
| ISICitedReferencesCount | 8 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000230463000040&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 1063-6897 |
| IngestDate | Fri Jul 11 10:33:19 EDT 2025 Wed Aug 27 02:17:21 EDT 2025 Wed Jan 31 06:47:37 EST 2024 Wed Jan 31 06:45:01 EST 2024 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MeetingName | ISCA05: The 32nd Annual International Symposium on Computer Architecture 2005 |
| MergedId | FETCHMERGED-LOGICAL-a272t-51a3054e8fa99439e6ec625e0caa027cb10d8e0fc935b553917ca10163a1cd263 |
| Notes | SourceType-Conference Papers & Proceedings-1 ObjectType-Conference Paper-1 content type line 25 |
| PQID | 31174533 |
| PQPubID | 23500 |
| PageCount | 12 |
| ParticipantIDs | ieee_primary_1431580 acm_books_10_1109_ISCA_2005_25 acm_books_10_1109_ISCA_2005_25_brief proquest_miscellaneous_31174533 |
| PublicationCentury | 2000 |
| PublicationDate | 20050501 20050000 20050604 |
| PublicationDateYYYYMMDD | 2005-05-01 2005-01-01 2005-06-04 |
| PublicationDate_xml | – month: 05 year: 2005 text: 20050501 day: 01 |
| PublicationDecade | 2000 |
| PublicationPlace | Washington, DC, USA |
| PublicationPlace_xml | – name: Washington, DC, USA |
| PublicationSeriesTitle | ACM Conferences |
| PublicationTitle | 32nd International Symposium on Computer Architecture (ISCA'05) |
| PublicationTitleAbbrev | ISCA |
| PublicationYear | 2005 |
| Publisher | IEEE Computer Society IEEE |
| Publisher_xml | – name: IEEE Computer Society – name: IEEE |
| SSID | ssj0000451212 ssj0019956 |
| Score | 1.6945654 |
| Snippet | In this paper, we develop the first feasibly implementable scheme for end-to-end dynamic verification of multithreaded memory systems. For multithreaded... In this paper, we develop the first feasibly implemental scheme for end-to-end dynamic verification of multithreaded memory systems. For multithreaded... |
| SourceID | proquest ieee acm |
| SourceType | Aggregation Database Publisher |
| StartPage | 482 |
| SubjectTerms | Bandwidth Bit error rate Coherence Computer architecture Computer science Computer systems organization -- Architectures -- Parallel architectures -- Multiple instruction, multiple data Control systems General and reference -- Cross-computing tools and techniques -- Design Hardware Hardware -- Electronic design automation -- High-level and register-transfer level synthesis Hardware -- Hardware validation -- Functional verification Hardware -- Integrated circuits Hardware -- Integrated circuits -- Logic circuits -- Sequential circuits Hardware -- Integrated circuits -- Semiconductor memory Multiprocessor interconnection networks Protocols System recovery |
| Title | Dynamic Verification of Sequential Consistency |
| URI | https://ieeexplore.ieee.org/document/1431580 https://www.proquest.com/docview/31174533 |
| WOSCitedRecordID | wos000230463000040&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEB5q8eCpaivWR91Dj2677yRHqRa9lIIKvYVskoWC7kofgv_emWwfB0XwtgsbWCaPmW8y830Afc1yDNli5YtIRX6iNPdzbpif6YR6BtAhCe3EJthkwmczMW3A7a4Xxlrris_sgB7dXb6p9JpSZUP07WHKEaAfMJbVvVq7fArxpER76ijqPHadReiC_YwT_R9BdoHhBgu2zDvbd76riBfDp-fRXZ1qIfXsA6XfN7orPw5r54HGrf_9-zF09q183nTnpE6gYctTaG21HLzN1m7D4L6WpvdwaVP1kJswryq8utYaz4E3T1Mx7ZKC7K8OvI4fXkaP_kZLwVcRi1Z-Girc2YnlhRICgxCbWY3QxwZaKUSmOg8Dw21QaBGneZrGiOK0ImQfq1CbKIvPoFlWpT0Hj8Q5osKK3KgkMUmWE22cNiHXhhVhwrrQQ6tJAglL6TBGICSZlSQvUxmlXej__YHMF3NbdKFNZpQfNe2G3FiwCzfbeZC4Feh-Q5W2Wi9lHCK8wvD14veBl3DkeFdd_uQKmqvF2l7Dof5czZeLnltN39P9vzg |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LS8NAEB5qFfRUtYr10ebg0Wiy2SS7R6mWFmspqNDbstlsQNBW-hD8985s-jgogrcEshBmHzPf7Mz3AVyaNMOQLdK-ZJr5XBvhZyJP_cRw6hlAhySNE5tIBwMxGslhBa7WvTDWWld8Zq_p0d3l5xOzoFTZDfr2MBYI0LdjzllQdmutMyrElMI25FHUe-x6i9AJ-4kgAkAC7RIDjjRYce-s3sW6Jl7e9J7at2WyhfSzt7R5Xyqv_DiunQ_q1P739_twtGnm84ZrN3UAFTs-hNpKzcFbbu46XN-V4vQeLm6qH3JT5k0Kr6y2xpPgzTNUTjujMPvrCF4698_trr9UU_A1S9ncj0ONe5tbUWgpMQyxiTUIfmxgtEZsarIwyIUNCiOjOIvjCHGc0YTtIx2anCXRMVTHk7E9AY_kOVhhZZZrznOeZEQcZ_JQmDwtQp42oIlWUwQTZsqhjEAqMiuJXsaKxQ24_PsDlU1fbdGAOplRfZTEG2ppwQa0VvOgcDPQDYce28lipqIQARYGsKe_D2zBbvf5sa_6vcHDGew5FlaXTTmH6ny6sBewYz7nr7Np062sb_s9wn8 |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=International+Symposium+on+Computer+Architecture%3A+Proceedings+of+the+32nd+annual+international+symposium+on+Computer+Architecture%3B+04-08+June+2005&rft.atitle=Dynamic+Verification+of+Sequential+Consistency&rft.au=Meixner%2C+Albert&rft.au=Sorin%2C+Daniel+J&rft.date=2005-06-04&rft.isbn=9780769522708&rft.issn=1063-6897&rft.spage=482&rft.epage=493&rft_id=info:doi/10.1109%2FISCA.2005.25&rft.externalDBID=NO_FULL_TEXT |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1063-6897&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1063-6897&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1063-6897&client=summon |