Optimal clustering for delay minimization

This paper addresses the problem of circuit clustering for delay minimization, subject to capacity constraints. We use the general delay model, for which only heuristic solutions were known. We present an optimal polynomial time algorithm for combinational circuits under this model. Our algorithm ca...

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Vydané v:30th ACM/IEEE Design Automation Conference s. 309 - 314
Hlavní autori: Rajaraman, Rajmohan, Wong, D. F.
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: New York, NY, USA ACM 01.07.1993
Edícia:ACM Conferences
Predmet:
Bridge circuits
Clustering algorithms
Combinational circuits
Delay effects
Hardware > Electronic design automation > Physical design (EDA) > Partitioning and floorplanning
Hardware > Integrated circuits > Logic circuits > Combinational circuits
Hardware > Very large scale integration design > Application-specific VLSI designs
Integrated circuit interconnections
Joining processes
Mathematics of computing > Discrete mathematics > Graph theory > Network flows
Minimization
Partitioning algorithms
Polynomials
Theory of computation > Computational complexity and cryptography
Theory of computation > Computational complexity and cryptography > Complexity classes
Theory of computation > Design and analysis of algorithms > Graph algorithms analysis > Network flows
Theory of computation > Randomness, geometry and discrete structures
Timing
ISBN:9780897915779, 0897915771
ISSN:0738-100X
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Shrnutí:This paper addresses the problem of circuit clustering for delay minimization, subject to capacity constraints. We use the general delay model, for which only heuristic solutions were known. We present an optimal polynomial time algorithm for combinational circuits under this model. Our algorithm can be generalized to solve the problem under any monotone clustering constraint.
Bibliografia:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780897915779
0897915771
ISSN:0738-100X
DOI:10.1145/157485.164907