Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices

Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on probabilistic transfer matrices (PTMs). In particular, we apply them to evaluate circuit reliability in the presence of s...

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Bibliographic Details
Published in:Design, Automation and Test in Europe pp. 282 - 287
Main Authors: Krishnaswamy, Smita, Viamontes, George F., Markov, Igor L., Hayes, John P.
Format: Conference Proceeding
Language:English
Published: Washington, DC, USA IEEE Computer Society 07.03.2005
IEEE
Series:ACM Conferences
Subjects:
Atmospheric modeling
Circuit analysis
Computer architecture
Data mining
Hardware > Hardware test
Hardware > Hardware validation > Functional verification
Hardware > Robustness
Hardware > Very large scale integration design
Logic circuits
Mathematics of computing > Mathematical analysis > Numerical analysis > Computations on matrices
Neutrons
Observability
Power system reliability
Probability
Tensile stress
ISBN:9780769522883, 0769522882
ISSN:1530-1591
Online Access:Get full text
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Summary:Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on probabilistic transfer matrices (PTMs). In particular, we apply them to evaluate circuit reliability in the presence of soft errors, which involves combining the PTMs of gates to form an overall circuit PTM. Information such as output probabilities, the overall probability of error, and signal observability can then be extracted from the circuit PTM. We employ algebraic decision diagrams (ADDs) to improve the efficiency of PTM operations. A particularly challenging technical problem, solved in our work, is to simultaneously extend tensor products and matrix multiplication in terms of ADDs to non-square matrices. Our PTM-based method enables accurate evaluation of reliability for moderately large circuits and can be extended by circuit partitioning. To demonstrate the power of the PTM approach, we apply it to several problems in fault-tolerant design and reliability improvement.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780769522883
0769522882
ISSN:1530-1591
DOI:10.1109/DATE.2005.47