The design and use of simplepower a cycle-accurate energy estimation tool
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the effect of high-level algorithmic, architectural, and compilation trade-offs on energy. An execution-driven, cycle-accurate RT lev el energy estimation tool that uses transition sensitive ene...
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| Veröffentlicht in: | 37th Design Automation Conference, 2000 S. 340 - 345 |
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| Abstract | In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the effect of high-level algorithmic, architectural, and compilation trade-offs on energy. An execution-driven, cycle-accurate RT lev el energy estimation tool that uses transition sensitive energy models forms the cornerstone of this framework. SimplePower also pro vides the energy consumed in the memory system and on-chip buses using analytical energy models.
We presen t the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a pow er-conscious post compilation optimization (register relabeling) on the datapath, memory and on-chip bus energy, respectively. We find that these three optimizations reduce the energy by 18-36% in the datapath, 62% in the memory system and 12% in the instruction cache data bus, respectively. |
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| AbstractList | In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the effect of high-level algorithmic, architectural, and compilation trade-offs on energy. An execution-driven, cycle-accurate RT lev el energy estimation tool that uses transition sensitive energy models forms the cornerstone of this framework. SimplePower also pro vides the energy consumed in the memory system and on-chip buses using analytical energy models.
We presen t the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a pow er-conscious post compilation optimization (register relabeling) on the datapath, memory and on-chip bus energy, respectively. We find that these three optimizations reduce the energy by 18-36% in the datapath, 62% in the memory system and 12% in the instruction cache data bus, respectively. |
| Author | Kandemir, M. Irwin, M. J. Ye, W. Vijaykrishnan, N. |
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| Snippet | In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the effect of high-level algorithmic, architectural,... |
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| SubjectTerms | Algorithm design and analysis Applied computing -- Physical sciences and engineering -- Engineering Computer systems organization -- Dependable and fault-tolerant systems and networks Design optimization Embedded software Energy consumption General and reference -- Cross-computing tools and techniques -- Performance Hardware -- Electronic design automation -- Methodologies for EDA Hardware -- Integrated circuits -- Logic circuits -- Arithmetic and datapath circuits Hardware -- Integrated circuits -- Logic circuits -- Design modules and hierarchy Hardware -- Robustness Networks -- Network performance evaluation Permission Power measurement Power system modeling Process design Registers Software tools |
| Subtitle | a cycle-accurate energy estimation tool |
| Title | The design and use of simplepower |
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