A Tree Based Router Search Engine Architecture with Single Port Memories

Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this results in unevenly distributed memory. To address this imbalance, conventional approaches use either complex dynamic memory a...

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Bibliographic Details
Published in:32nd International Symposium on Computer Architecture (ISCA'05) pp. 123 - 133
Main Authors: Baboescu, Florin, Tullsen, Dean M., Rosu, Grigore, Singh, Sumeet
Format: Conference Proceeding
Language:English
Published: Washington, DC, USA IEEE Computer Society 01.05.2005
IEEE
Series:ACM Conferences
Subjects:
Computer architecture
Computer science
Computer systems organization > Architectures > Other architectures
Computing methodologies > Artificial intelligence > Search methodologies
Computing methodologies > Artificial intelligence > Search methodologies > Discrete space search
Computing methodologies > Artificial intelligence > Search methodologies > Game tree search
Computing methodologies > Modeling and simulation > Model development and analysis > Modeling methodologies
Costs
General and reference > Cross-computing tools and techniques > Design
General and reference > Cross-computing tools and techniques > Performance
Hardware > Communication hardware, interfaces and storage
Hardware > Integrated circuits
High-speed networks
Mathematics of computing > Discrete mathematics > Graph theory > Trees
Microarchitecture
Networks
Networks > Network components > Intermediate nodes > Routers
Pipelines
Search engines
Throughput
Virtual private networks
ISBN:076952270X, 9780769522708
ISSN:1063-6897
Online Access:Get full text
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Summary:Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this results in unevenly distributed memory. To address this imbalance, conventional approaches use either complex dynamic memory allocation schemes or over-provision each of the pipeline stages. This paper describes the microarchitecture of a novel network search processor which provides both high execution throughput and balanced memory distribution by dividing the tree into subtrees and allocating each subtree separately, allowing searches to begin at any pipeline stage. The architecture is validated by implementing and simulating state of the art solutions for IPv4 lookup, VPN forwarding and packet classification. The new pipeline scheme and memory allocator can provide searches with a memory allocation efficiency that is within 1% of non-pipelined schemes.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:076952270X
9780769522708
ISSN:1063-6897
DOI:10.1109/ISCA.2005.7