Automatic synthesis of Boolean equations using programmable array logic

We present a methodology and prototype system that automates the synthesis of combinational logic using Programmable Array Logic chips (PALs). (FOOTNOTE: PAL is a trademark of Monolithic Memories Inc.) The input is a set of boolean equations and a database of available PALs. The output is a set of e...

Full description

Saved in:
Bibliographic Details
Published in:26th ACM/IEEE Design Automation Conference pp. 283 - 289
Main Authors: Goré, R. P., Ramaamohanarao, K.
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 01.06.1989
Series:ACM Conferences
Subjects:
Automatic logic units
Boolean functions
Bridge circuits
Combinational circuits
Computer science
Equations
Hardware > Electronic design automation > High-level and register-transfer level synthesis
Hardware > Integrated circuits > Logic circuits > Combinational circuits
Hardware > Very large scale integration design
Logic devices
Permission
Pins
Programmable logic arrays
ISBN:0897913108, 9780897913102
ISSN:0738-100X
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We present a methodology and prototype system that automates the synthesis of combinational logic using Programmable Array Logic chips (PALs). (FOOTNOTE: PAL is a trademark of Monolithic Memories Inc.) The input is a set of boolean equations and a database of available PALs. The output is a set of equivalent equations, a set of chosen PALs and a mapping specifying which equations to implement on which PAL.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:0897913108
9780897913102
ISSN:0738-100X
DOI:10.1145/74382.74430