NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator
Graph Neural Networks (GNNs) are emerging as a formidable tool for processing non-euclidean data across various domains, ranging from social network analysis to bioinformatics. Despite their effectiveness, their adoption has not been pervasive because of scalability challenges associated with large-...
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| Veröffentlicht in: | 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) S. 946 - 960 |
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29.06.2024
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| Abstract | Graph Neural Networks (GNNs) are emerging as a formidable tool for processing non-euclidean data across various domains, ranging from social network analysis to bioinformatics. Despite their effectiveness, their adoption has not been pervasive because of scalability challenges associated with large-scale graph datasets, particularly when leveraging message passing. They exhibit irregular sparsity patterns, resulting in unbalanced compute resource utilization. Prior accelerators investigating Gustavson's technique adopted look-ahead buffers for prefetching data, aiming to prevent compute stalls. However, these solutions lead to inefficient use of the on-chip memory, leading to redundant data residing in cache.To tackle these challenges, we introduce NeuraChip, a novel GNN spatial accelerator based on Gustavson's algorithm. NeuraChip decouples the multiplication and addition computations in sparse matrix multiplication. This separation allows for independent exploitation of their unique data dependencies, facilitating efficient resource allocation. We introduce a rolling eviction strategy to mitigate data idling in on-chip memory as well as address the prevalent issue of memory bloat in sparse graph computations. Furthermore, the compute resource load balancing is achieved through a dynamic reseeding hash-based mapping, ensuring uniform utilization of computing resources agnostic of sparsity patterns. Finally, we present NeuraSim, an open-source, cycle-accurate, multi-threaded, modular simulator for comprehensive performance analysis.Overall, NeuraChip presents a significant improvement, yielding an average speedup of 22.1 \times over Intel's MKL, 17.1 \times over NVIDIA's cuSPARSE, 16.7 \times over AMD's hipSPARSE, and 1.5 \times over prior state-of-the-art SpGEMM accelerator and 1.3 \times over GNN accelerator. The source code for our open-sourced simulator and performance visualizer is publicly accessible on GitHub 1 . CCS CONCEPTS * Computer systems organization → Multicore architectures; Interconnection architectures; * Computing methodologies → Neural networks; * Theory of computation → Graph algorithms analysis; * Hardware → Hardware accelerators. 1 https://github.com/NeuraChip/neurachip |
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| AbstractList | Graph Neural Networks (GNNs) are emerging as a formidable tool for processing non-euclidean data across various domains, ranging from social network analysis to bioinformatics. Despite their effectiveness, their adoption has not been pervasive because of scalability challenges associated with large-scale graph datasets, particularly when leveraging message passing. They exhibit irregular sparsity patterns, resulting in unbalanced compute resource utilization. Prior accelerators investigating Gustavson's technique adopted look-ahead buffers for prefetching data, aiming to prevent compute stalls. However, these solutions lead to inefficient use of the on-chip memory, leading to redundant data residing in cache.To tackle these challenges, we introduce NeuraChip, a novel GNN spatial accelerator based on Gustavson's algorithm. NeuraChip decouples the multiplication and addition computations in sparse matrix multiplication. This separation allows for independent exploitation of their unique data dependencies, facilitating efficient resource allocation. We introduce a rolling eviction strategy to mitigate data idling in on-chip memory as well as address the prevalent issue of memory bloat in sparse graph computations. Furthermore, the compute resource load balancing is achieved through a dynamic reseeding hash-based mapping, ensuring uniform utilization of computing resources agnostic of sparsity patterns. Finally, we present NeuraSim, an open-source, cycle-accurate, multi-threaded, modular simulator for comprehensive performance analysis.Overall, NeuraChip presents a significant improvement, yielding an average speedup of 22.1 \times over Intel's MKL, 17.1 \times over NVIDIA's cuSPARSE, 16.7 \times over AMD's hipSPARSE, and 1.5 \times over prior state-of-the-art SpGEMM accelerator and 1.3 \times over GNN accelerator. The source code for our open-sourced simulator and performance visualizer is publicly accessible on GitHub 1 . CCS CONCEPTS * Computer systems organization → Multicore architectures; Interconnection architectures; * Computing methodologies → Neural networks; * Theory of computation → Graph algorithms analysis; * Hardware → Hardware accelerators. 1 https://github.com/NeuraChip/neurachip |
| Author | Shivdikar, Kaustubh Jayaweera, Malith Kim, John Kaeli, David Joshi, Ajay Jonatan, Gilbert Agostini, Nicolas Bohm Abellan, Jose L. |
| Author_xml | – sequence: 1 givenname: Kaustubh surname: Shivdikar fullname: Shivdikar, Kaustubh email: shivdikar.k@northeastern.edu organization: Northeastern University – sequence: 2 givenname: Nicolas Bohm surname: Agostini fullname: Agostini, Nicolas Bohm email: bohmagostini.n@northeastern.edu organization: Northeastern University – sequence: 3 givenname: Malith surname: Jayaweera fullname: Jayaweera, Malith email: malithjayaweera.d@northeastern.edu organization: Northeastern University – sequence: 4 givenname: Gilbert surname: Jonatan fullname: Jonatan, Gilbert email: gilbertjonatan@kaist.ac.kr organization: KAIST – sequence: 5 givenname: Jose L. surname: Abellan fullname: Abellan, Jose L. email: jlabellan@um.es organization: Universidad de Murcia – sequence: 6 givenname: Ajay surname: Joshi fullname: Joshi, Ajay email: joshi@bu.edu organization: Boston University – sequence: 7 givenname: John surname: Kim fullname: Kim, John email: jjk12@kaist.ac.kr organization: KAIST – sequence: 8 givenname: David surname: Kaeli fullname: Kaeli, David email: d.kaeli@northeastern.edu organization: Northeastern University |
| BookMark | eNpFj8FKw0AURUdQUGv-oIv5gdQ3mcy8GXclalsodVEFd-U1eTGBNAmZFPHvjSi4uvfC4cC9FZdt17IQcwULpcDfb_bZ0nhAXCSQpAsAQH0hIo_eaQM6scapaxGFUB_BgkeNztyI9x2fB8qqun-Qyzznhgca6_ZDrnY7mXWn_jxOu2uD_KzHSpJcU6jiIwUu5CPn3blvprbvJ4iaf0M33ImrkprA0V_OxNvz02u2jrcvq0223MaUGDfGZaEZy9zlirwHTjEh9JYtaDDOKGsL6zU7hpLSwhiLSU4erQZyWGit9EzMf701Mx_6oT7R8HVQPxctov4GfRBShQ |
| CODEN | IEEPAD |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO |
| DOI | 10.1109/ISCA59077.2024.00073 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP) 1998-present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| EISBN | 9798350326581 |
| EndPage | 960 |
| ExternalDocumentID | 10609677 |
| Genre | orig-research |
| GrantInformation_xml | – fundername: Samsung funderid: 10.13039/100004358 |
| GroupedDBID | 6IE 6IH ACM ALMA_UNASSIGNED_HOLDINGS CBEJK RIE RIO |
| ID | FETCH-LOGICAL-a258t-fd3e7fc8c1a990e472a796e6030585166d693e8e0fa4d55672ca97630a87d3313 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 2 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001290320700063&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Aug 27 02:34:53 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-a258t-fd3e7fc8c1a990e472a796e6030585166d693e8e0fa4d55672ca97630a87d3313 |
| PageCount | 15 |
| ParticipantIDs | ieee_primary_10609677 |
| PublicationCentury | 2000 |
| PublicationDate | 2024-June-29 |
| PublicationDateYYYYMMDD | 2024-06-29 |
| PublicationDate_xml | – month: 06 year: 2024 text: 2024-June-29 day: 29 |
| PublicationDecade | 2020 |
| PublicationTitle | 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) |
| PublicationTitleAbbrev | ISCA |
| PublicationYear | 2024 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| SSID | ssib060973785 |
| Score | 2.2816432 |
| Snippet | Graph Neural Networks (GNNs) are emerging as a formidable tool for processing non-euclidean data across various domains, ranging from social network analysis... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 946 |
| SubjectTerms | Computer architecture Decoupled Computations Graph neural networks Graph Neural Networks (GNN) Hardware-software co-design On-chip Memory Organizations Prefetching Scalability Social networking (online) Source coding Sparse Matrix Multiplication (SpGEMM) Spatial Accelerators |
| Title | NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator |
| URI | https://ieeexplore.ieee.org/document/10609677 |
| WOSCitedRecordID | wos001290320700063&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV09T8MwELUoYmACRBHf8sAaSOzY57BVhVKWqBIgdauM7dBKKK36we_nzmkpCwOblSGRzrbu3uXee4zd2OrduYqmp4RHgEIcXQOVTDJvlTXam-DyaDYBZWmGw2KwJqtHLkwIIQ6fhVtaxn_5fupW1CrDG66x4gZosRYANGStzeHRpDsDRq3pcVla3D2_dDsKwR8gDBQkkp2SO_ovE5WYQ3oH__z6IWtv2Xh88JNnjthOqI_ZkFQ1bHc8md3zjnOYPGgr6w_-VJa8sWpoenGcOq3c8r5djBPKWZ4_IORczT5xRYbEeAC3b5jO2-yt9_ja7Sdrl4TECmWWSeVlgMoZl1nMLCEHYaHQQdNNxnJKa68LGUxIK5t7pTQIZ7EGkak14KXM5Anbrad1OGVcRuHSDHGrCDnisoJ8OLBecFhVeq_gjLUpLKNZI4Qx2kTk_I_nF2yfIk-TVaK4ZLvL-SpcsT33tZws5tdx-74BK9SZ_w |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3JTsMwELWgIMEJEEXs-MA1kNjxEm5VWVpRokoUqbfK2A6thNKqC9_PjNNSLhy4WTkkksfWmzeZN4-Qa1O8W1tg9xRzQFBQo6tVwaPEGWG0dNrbNJhNqDzX_X7WXYrVgxbGex-az_wNLsO_fDe2CyyVwQ2XkHErtUm2RJqypJJrrY6PxMkzSoulQC6Js9v2a7MhgP4pIIIMx2TH6I_-y0YloMjj3j-_v0_qaz0e7f4gzQHZ8OUh6eNcDdMcjiZ3tGEtwAcGs_ygT3lOK7OGqhpHsdZKDW2Z2TBC1HL0HkjnYvIJK7QkhiO4fsN4Widvjw-9Zita-iREhgk9jwrHvSqstokBbPGpYkZl0ku8y5BQSelkxr32cWFSJ4RUzBrIQnhstHKcJ_yI1Mpx6Y8J5WF0aQLMlfkUmFmGThyQMVjIK50T6oTUcVsGk2oUxmC1I6d_PL8iO63eS2fQaefPZ2QXo4B9Viw7J7X5dOEvyLb9mo9m08sQym9hc51G |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2024+ACM%2FIEEE+51st+Annual+International+Symposium+on+Computer+Architecture+%28ISCA%29&rft.atitle=NeuraChip%3A+Accelerating+GNN+Computations+with+a+Hash-based+Decoupled+Spatial+Accelerator&rft.au=Shivdikar%2C+Kaustubh&rft.au=Agostini%2C+Nicolas+Bohm&rft.au=Jayaweera%2C+Malith&rft.au=Jonatan%2C+Gilbert&rft.date=2024-06-29&rft.pub=IEEE&rft.spage=946&rft.epage=960&rft_id=info:doi/10.1109%2FISCA59077.2024.00073&rft.externalDocID=10609677 |