Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore

Existing tiled manycore architectures propose to convert abundant silicon resources into general-purpose parallel processors with unmatched computational density and programmability. However, as we approach 100 K cores in one chip, conventional manycore architectures struggle to navigate three key a...

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Bibliographic Details

Published in:	2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) pp. 770 - 784
Main Authors:	Jung, Dai Cheol, Ruttenberg, Max, Gao, Paul, Davidson, Scott, Petrisko, Daniel, Li, Kangli, Kamath, Aditya K, Cheng, Lin, Xie, Shaolin, Pan, Peitian, Zhao, Zhongyuan, Yue, Zichao, Veluri, Bandhav, Muralitharan, Sripathi, Sampson, Adrian, Lumsdaine, Andrew, Zhang, Zhiru, Batten, Christopher, Oskin, Mark, Richmond, Dustin, Taylor, Michael Bedford
Format:	Conference Proceeding
Language:	English
Published:	IEEE 29.06.2024
Subjects:	Computer architecture Instruction sets manycore architecture open-source hardware Parallel processing parallel programming RISC-V Scalability Silicon Source coding Voltage
Online Access:	Get full text
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