Native DRAM Cache: Re-architecting DRAM as a Large-Scale Cache for Data Centers
Contemporary data center CPUs are experiencing an unprecedented surge in core count. This trend necessitates scrutinized Last-Level Cache (LLC) strategies to accommodate increasing capacity demands. While DRAM offers significant capacity, using it as a cache poses challenges related to latency and e...
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| Veröffentlicht in: | 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) S. 1144 - 1156 |
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29.06.2024
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| Abstract | Contemporary data center CPUs are experiencing an unprecedented surge in core count. This trend necessitates scrutinized Last-Level Cache (LLC) strategies to accommodate increasing capacity demands. While DRAM offers significant capacity, using it as a cache poses challenges related to latency and energy. This paper introduces Native DRAM Cache (NDC), a novel DRAM architecture specifically designed to operate as a cache. NDC features innovative approaches, such as conducting tag matching and way selection within a DRAM subarray and repurposing existing precharge transistors for tag matching. These innovations facilitate Caching-In-Memory (CIM) and enable NDC to serve as a high-capacity LLC with high set-associativity, low-latency, high-throughput, and low-energy. Our evaluation demonstrates that NDC significantly outperforms state-of-the-art DRAM cache solutions, enhancing performance by \mathbf{2.8 \%} / \mathbf{52.5 \%} / \mathbf{44.2 \%} (up to 8.4 \% / 140.6 \% / 85.5 \%) in SPEC/NPB/GAP benchmark suites, respectively. |
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| AbstractList | Contemporary data center CPUs are experiencing an unprecedented surge in core count. This trend necessitates scrutinized Last-Level Cache (LLC) strategies to accommodate increasing capacity demands. While DRAM offers significant capacity, using it as a cache poses challenges related to latency and energy. This paper introduces Native DRAM Cache (NDC), a novel DRAM architecture specifically designed to operate as a cache. NDC features innovative approaches, such as conducting tag matching and way selection within a DRAM subarray and repurposing existing precharge transistors for tag matching. These innovations facilitate Caching-In-Memory (CIM) and enable NDC to serve as a high-capacity LLC with high set-associativity, low-latency, high-throughput, and low-energy. Our evaluation demonstrates that NDC significantly outperforms state-of-the-art DRAM cache solutions, enhancing performance by \mathbf{2.8 \%} / \mathbf{52.5 \%} / \mathbf{44.2 \%} (up to 8.4 \% / 140.6 \% / 85.5 \%) in SPEC/NPB/GAP benchmark suites, respectively. |
| Author | Ryu, Yesin Jung, Giyong Kim, Yoojin Ahn, Jung Ho Kim, Jungrae |
| Author_xml | – sequence: 1 givenname: Yesin surname: Ryu fullname: Ryu, Yesin email: yesin.ryu@samsung.com organization: Sungkyunkwan University,Suwon,Republic of Korea – sequence: 2 givenname: Yoojin surname: Kim fullname: Kim, Yoojin email: g24067yjs@g.skku.edu organization: Sungkyunkwan University,Suwon,Republic of Korea – sequence: 3 givenname: Giyong surname: Jung fullname: Jung, Giyong email: gajh@snu.ac.kr organization: Sungkyunkwan University,Suwon,Republic of Korea – sequence: 4 givenname: Jung Ho surname: Ahn fullname: Ahn, Jung Ho email: dale40@skku.edu organization: Seoul National University,Seoul,Republic of Korea – sequence: 5 givenname: Jungrae surname: Kim fullname: Kim, Jungrae email: jyk2498@g.skku.edu organization: Sungkyunkwan University,Suwon,Republic of Korea |
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| Snippet | Contemporary data center CPUs are experiencing an unprecedented surge in core count. This trend necessitates scrutinized Last-Level Cache (LLC) strategies to... |
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| SubjectTerms | Caching-In-Memory (CIM) Data centers DRAM Cache Energy consumption Energy resolution high-capacity LLC Metadata Random access memory Technological innovation |
| Title | Native DRAM Cache: Re-architecting DRAM as a Large-Scale Cache for Data Centers |
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