pSyncPIM: Partially Synchronous Execution of Sparse Matrix Operations for All-Bank PIM Architectures

Recent commercial incarnations of processing-in-memory (PIM) maintain the standard DRAM interface and employ the all-bank mode execution to maximize bank-level memory bandwidth. Such a synchronized all-bank PIM control can effectively manage conventional dense matrix-vector operations on evenly dist...

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Veröffentlicht in:	2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) S. 354 - 367
Hauptverfasser:	Baek, Daehyeon, Hwang, Soojin, Huh, Jaehyuk
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 29.06.2024
Schlagworte:	Bandwidth Compaction Computer architecture memory bandwidth predicated execution Process control processing-in-memory Random access memory Sparse matrices sparse matrix Vectors
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