Web-Based Simulator of Superscalar RISC-V Processors

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable proce...

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Vydáno v:SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis s. 1676 - 1684
Hlavní autoři: Jaros, Jiri, Majer, Michal, Horky, Jakub, Vavra, Jan
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 17.11.2024
Témata:
Codes
Computer architecture
HW-SW Co-design
Optimization
Processor Simulator
Program processors
RISC-V
Runtime
Semiconductor device measurement
Software development management
Source coding
Superscalar Processor
Systems architecture
Vectors
Web Application
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Shrnutí:Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.
DOI:10.1109/SCW63240.2024.00209