Web-Based Simulator of Superscalar RISC-V Processors

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable proce...

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Bibliographic Details

Published in:	SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis pp. 1676 - 1684
Main Authors:	Jaros, Jiri, Majer, Michal, Horky, Jakub, Vavra, Jan
Format:	Conference Proceeding
Language:	English
Published:	IEEE 17.11.2024
Subjects:	Codes Computer architecture HW-SW Co-design Optimization Processor Simulator Program processors RISC-V Runtime Semiconductor device measurement Software development management Source coding Superscalar Processor Systems architecture Vectors Web Application
Online Access:	Get full text
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