Directed-Logical Testing for Functional Verification of Microprocessors

The length of the microprocessor development cycle is largely determined by functional verification, where contemporary practice relies primarily on constraint-based random stimulus generation to drive a simulation-based methodology. However, formal methods are, in particular, gaining wider adoption...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:2008 6th IEEE/ACM International Conference on Formal Methods and Models for Codesign s. 89 - 100
Hlavní autoři: Katelman, M., Meseguer, J., Escobar, S.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: Washington, DC, USA IEEE Computer Society 01.06.2008
IEEE
Edice:ACM Conferences
Témata:
Assembly
Automatic testing
Computer science
Drives
Hardware design languages
Logic testing
Microprocessors
Pipelines
Random number generation
Scalability
Theory of computation
Theory of computation > Formal languages and automata theory
Theory of computation > Formal languages and automata theory > Formalisms
Theory of computation > Formal languages and automata theory > Formalisms > Rewrite systems
Theory of computation > Formal languages and automata theory > Grammars and context-free languages
Theory of computation > Semantics and reasoning
Theory of computation > Semantics and reasoning > Program semantics
ISBN:1424424178, 9781424424177
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Abstract The length of the microprocessor development cycle is largely determined by functional verification, where contemporary practice relies primarily on constraint-based random stimulus generation to drive a simulation-based methodology. However, formal methods are, in particular, gaining wider adoption and are seen as having potential to bridge large gaps left by current techniques. And many gaps still remain. In this paper we propose directed- logical testing: a new method of stimulus generation based on purely logical techniques (i.e. formal methods). As far as we know, our methodology represents the first end-to-end mathematical formalization of the stimulus generation problem. Therefore, a major contribution of this paper is the definition of a class of logical propositions that relate the actual microprocessor implementation, the assembly program stimulus, and a coverage goal. These propositions are given in rewriting logic, and use the idea of rewriting semantics to automatically formalize within a common logical framework the microprocessor implementation and assembly programs. To solve these propositions, we demonstrate how narrowing and user-defined narrowing strategies can be used as a scalable logical framework. In addition, we describe two classes of effective strategies that can be used for many microprocessors and common coverage goals. Finally, we describe a prototype tool implementation and present empirical data to demonstrate the feasibility of our methodology. Since narrowing and user-defined narrowing strategies within rewriting logic do not yet have tool support, our prototype tool uses standard rewriting and user-defined rewriting strategies to simulate narrowing.
AbstractList The length of the microprocessor development cycle is largely determined by functional verification, where contemporary practice relies primarily on constraint-based random stimulus generation to drive a simulation-based methodology. However, formal methods are, in particular, gaining wider adoption and are seen as having potential to bridge large gaps left by current techniques. And many gaps still remain. In this paper we propose directed- logical testing: a new method of stimulus generation based on purely logical techniques (i.e. formal methods). As far as we know, our methodology represents the first end-to-end mathematical formalization of the stimulus generation problem. Therefore, a major contribution of this paper is the definition of a class of logical propositions that relate the actual microprocessor implementation, the assembly program stimulus, and a coverage goal. These propositions are given in rewriting logic, and use the idea of rewriting semantics to automatically formalize within a common logical framework the microprocessor implementation and assembly programs. To solve these propositions, we demonstrate how narrowing and user-defined narrowing strategies can be used as a scalable logical framework. In addition, we describe two classes of effective strategies that can be used for many microprocessors and common coverage goals. Finally, we describe a prototype tool implementation and present empirical data to demonstrate the feasibility of our methodology. Since narrowing and user-defined narrowing strategies within rewriting logic do not yet have tool support, our prototype tool uses standard rewriting and user-defined rewriting strategies to simulate narrowing.
Author Meseguer, J.
Katelman, M.
Escobar, S.
Author_xml – sequence: 1
  givenname: M.
  surname: Katelman
  fullname: Katelman, M.
  organization: Dept. of Comput. Sci., Univ. of Illinois at Urbana, Champaign, IL
– sequence: 2
  givenname: J.
  surname: Meseguer
  fullname: Meseguer, J.
  organization: Dept. of Comput. Sci., Univ. of Illinois at Urbana, Champaign, IL
– sequence: 3
  givenname: S.
  surname: Escobar
  fullname: Escobar, S.
BookMark eNqVUMtuAjEMjNQitVC-gMt-QJcmm-zrWAGllUBcaK-R1-ugtLBByfbQv29W0A-oZckaj8eyZ8xuO9cRYzPB50Lw-mm72i52y3nGeTVXuSqLWt2wsVCZiinKasTGA1dzqZS4Y9MQPnkMlcuSF_dsvbSesKc23biDRTgmewq97Q6JcT55-e6wt66L7Q_y1sSBASbOJFuL3p29QwrB-fDARgaOgabXOmHvL6v94jXd7NZvi-dNClme96ks6qpoEHOBBiUCCmgNNBKpgLqIiAyByAVICaptM2naUsbrG-AlNVUlJ2x22WuJSJ-9PYH_0dfHI5tdWMCTbpz7ClpwPfikLz7pwYu_cd14SyaKHv8hkr-tbmxb
ContentType Conference Proceeding
Copyright 2008
Copyright_xml – notice: 2008
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/MEMCOD.2008.4547694
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList

Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Computer Science
EndPage 100
ExternalDocumentID 4547694
Genre orig-research
GroupedDBID 6IE
6IF
6IK
6IL
6IN
AAJGR
AARBI
ACM
ADPZR
ALMA_UNASSIGNED_HOLDINGS
APO
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
GUFHI
IERZE
OCL
RIE
RIL
AAWTH
LHSKQ
ID FETCH-LOGICAL-a255t-36986bcc51cfc3cac1adfab3ce6a96c1aefea151a33a4dd23fd73089ba07eb883
IEDL.DBID RIE
ISBN 1424424178
9781424424177
ISICitedReferencesCount 5
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000257113700011&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Aug 27 02:11:17 EDT 2025
Wed Jan 31 06:47:57 EST 2024
IsPeerReviewed false
IsScholarly false
LCCN 2008903441
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a255t-36986bcc51cfc3cac1adfab3ce6a96c1aefea151a33a4dd23fd73089ba07eb883
PageCount 12
ParticipantIDs acm_books_10_1109_MEMCOD_2008_4547694
acm_books_10_1109_MEMCOD_2008_4547694_brief
ieee_primary_4547694
PublicationCentury 2000
PublicationDate 20080601
2008-June
PublicationDateYYYYMMDD 2008-06-01
PublicationDate_xml – month: 06
  year: 2008
  text: 20080601
  day: 01
PublicationDecade 2000
PublicationPlace Washington, DC, USA
PublicationPlace_xml – name: Washington, DC, USA
PublicationSeriesTitle ACM Conferences
PublicationTitle 2008 6th IEEE/ACM International Conference on Formal Methods and Models for Codesign
PublicationTitleAbbrev MEMCOD
PublicationYear 2008
Publisher IEEE Computer Society
IEEE
Publisher_xml – name: IEEE Computer Society
– name: IEEE
SSID ssj0000453706
Score 1.429065
Snippet The length of the microprocessor development cycle is largely determined by functional verification, where contemporary practice relies primarily on...
SourceID ieee
acm
SourceType Publisher
StartPage 89
SubjectTerms Assembly
Automatic testing
Computer science
Drives
Hardware design languages
Logic testing
Microprocessors
Pipelines
Random number generation
Scalability
Theory of computation
Theory of computation -- Formal languages and automata theory
Theory of computation -- Formal languages and automata theory -- Formalisms
Theory of computation -- Formal languages and automata theory -- Formalisms -- Rewrite systems
Theory of computation -- Formal languages and automata theory -- Grammars and context-free languages
Theory of computation -- Semantics and reasoning
Theory of computation -- Semantics and reasoning -- Program semantics
Title Directed-Logical Testing for Functional Verification of Microprocessors
URI https://ieeexplore.ieee.org/document/4547694
WOSCitedRecordID wos000257113700011&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV09T8MwED2VioGpQIsoX_IAE4QmcRLbc2lhoKVDQd0i27FRB5Iqbfn92HFShMQAW5xYlnWx_e7Od-8ArjUVChMqPMpEZgwUEXpM48CjGhvlFJNACVEVmyDTKV0s2KwFd7tcGKVUFXym7u1jdZefFXJrXWUDSz6VsGgP9ghJXK7Wzp9iVBNM_KTJ3TLARGhD6VS3Sc06FPhsMBlNhi8PLpayHtbik_z4UWWlAplx53_TO4Ted7Yemu1w6AhaKj-GTlOuAdW7twuP7nhTmffszjs0txQb-TsyiisaG4BzfkH0Zlalrn15qNBoYoP2Vi6joCjXPXgdj-bDJ6-uo-BxYzBsPJwwmggp40BqiSWXAc80F1iqhLPEtJRW3CA_x5hHWRZinZl9b34e94kSlOITaOdFrk4BSWOt-DG3lDRxFPmcEWWGETL0BYt16PfhxsgwtQbCOq3sC5-lTtau4GUtoz7c_qlfKsql0n3oWmmnK0fA0Xw8-_31ORy4oA7rKrmA9qbcqkvYl5-b5bq8qlbNF9Kju40
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV07T8MwED6VggRTgRZRnh5gglAnzsOeC6WIpnQoqFtkOzbqQFv1we_HjtMiJAbY4sSyrPPju7vcfQdwpalQJKHCo0zkxkARgcc08T2qiVFOSeIrIYpiE0m_T0cjNqjA7SYXRilVBJ-pO_tY_MvPp3JlXWUtSz4Vs3ALtqMwDLDL1tp4VIxyQhIcr7O3DDQldE3qVLaTknfIx6yVPqTtl3sXTVkObBFKfvyos1LATKf2vwnuQ-M7Xw8NNkh0ABU1OYTaumADKs9vHR7dBadyr-duPDS0JBuTd2RUV9QxEOc8g-jN7EtdevPQVKPUhu3NXE7BdL5owGvnYdjuemUlBY8bk2HpkZjRWEgZ-VJLIrn0ea65IFLFnMWmpbTiBvs5ITzM84Do3Jx8s3wcJ0pQSo6gOplO1DEgaewVHHFLSmMWAXOWKDOMkAEWLNIBbsK1kWFmTYRFVlgYmGVO1q7kZSmjJtz8qV8m5mOlm1C30s5mjoJj_fHk99eXsNsdpr2s99R_PoU9F-JhHSdnUF3OV-ocduTncryYXxQ76AvFs77U
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Proceedings+of+the+Sixth+ACM%2FIEEE+International+Conference+on+Formal+Methods+and+Models+for+Co-Design&rft.atitle=Directed-Logical+Testing+for+Functional+Verification+of+Microprocessors&rft.series=ACM+Conferences&rft.date=2008-06-01&rft.pub=IEEE+Computer+Society&rft.isbn=1424424178&rft.spage=89&rft.epage=100&rft_id=info:doi/10.1109%2FMEMCOD.2008.4547694
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781424424177/lc.gif&client=summon&freeimage=true
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781424424177/mc.gif&client=summon&freeimage=true
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781424424177/sc.gif&client=summon&freeimage=true