Procedure placement using temporal ordering information

Instruction cache performance is very important to instruction fetch efficiency and overall processor performance. The layout of an executable has a substantial effect on the cache miss rate during execution. This means that the performance of an executable can be improved significantly by applying...

Full description

Saved in:
Bibliographic Details
Published in:Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture pp. 303 - 313
Main Authors: Gloy, Nikolas, Blackwell, Trevor, Smith, Michael D., Calder, Brad
Format: Conference Proceeding Journal Article
Language:English
Published: Washington, DC, USA IEEE Computer Society 01.01.1997
Series:ACM Conferences
Subjects:
Computer systems organization > Architectures > Parallel architectures > Very long instruction word
Computer systems organization > Architectures > Serial architectures > Complex instruction set computing
Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing
Computer systems organization > Dependable and fault-tolerant systems and networks
General and reference > Cross-computing tools and techniques > Performance
Mathematics of computing > Information theory
Mathematics of computing > Information theory > Coding theory
Mathematics of computing > Mathematical software
Networks > Network performance evaluation
Security and privacy > Cryptography > Mathematical foundations of cryptography
code layout
conflict misses
profiling
ISBN:0818679778, 9780818679773
ISSN:1072-4451
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Instruction cache performance is very important to instruction fetch efficiency and overall processor performance. The layout of an executable has a substantial effect on the cache miss rate during execution. This means that the performance of an executable can be improved significantly by applying a code-placement algorithm that minimizes instruction cache conflicts. We describe an algorithm for procedure placement, one type of code-placement algorithm, that significantly differs from previous approaches in the type of information used to drive the placement algorithm. In particular, we gather temporal ordering information that summarizes the interleaving of procedures in a program trace. Our algorithm uses this information along with cache configuration and procedure size information to better estimate the conflict cost of a potential procedure ordering. We compare the performance of our algorithm with previously published procedure-placement algorithms and show noticeable improvements in the instruction cache behavior.
Bibliography:SourceType-Scholarly Journals-2
ObjectType-Feature-2
ObjectType-Conference Paper-1
content type line 23
SourceType-Conference Papers & Proceedings-1
ObjectType-Article-3
ISBN:0818679778
9780818679773
ISSN:1072-4451
DOI:10.5555/266800.266829