Modulo scheduling with integrated register spilling for clustered VLIW architectures

Clustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers and functional units are grouped in clusters so that new instructions are neede...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture s. 160 - 169
Hlavní autoři: Zalamea, Javier, Llosa, Josep, Ayguadé, Eduard, Valero, Mateo
Médium: Konferenční příspěvek Journal Article
Jazyk:angličtina
Vydáno: Washington, DC, USA IEEE Computer Society 01.01.2001
Edice:ACM Conferences
Témata:
ISBN:0769513697, 9780769513690
ISSN:1072-4451
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Popis
Shrnutí:Clustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers and functional units are grouped in clusters so that new instructions are needed to move data between them. New aggressive instruction scheduling techniques are required to minimize the negative effect of resource clustering and delays in moving data around.In this paper we present a novel software pipelining technique that performs instruction scheduling with reduced register requirements, register allocation, register spilling and inter-cluster communication in a single step. The algorithm uses limited backtracking to reconsider previously taken decisions. This backtracking provides the algorithm with additional possibilities for obtaining high throughput schedules with low spill code requirements for clustered architectures. We show that the proposed approach outperforms previously proposed techniques and that it is very scalable independently of the number of clusters, the number of communication buses and communication latency. The paper also includes an exploration of some parameters in the design of future clustered VLIW cores.
Bibliografie:SourceType-Scholarly Journals-2
ObjectType-Feature-2
ObjectType-Conference Paper-1
content type line 23
SourceType-Conference Papers & Proceedings-1
ObjectType-Article-3
ISBN:0769513697
9780769513690
ISSN:1072-4451
DOI:10.5555/563998.564020