Zalamea, J., Llosa, J., Ayguadé, E., & Valero, M. (2001, January). Modulo scheduling with integrated register spilling for clustered VLIW architectures. Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, 160-169. https://doi.org/10.5555/563998.564020
Citácia podle Chicago (17th ed.)Zalamea, Javier, Josep Llosa, Eduard Ayguadé, a Mateo Valero. "Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures." Proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture Jan. 2001: 160-169. https://doi.org/10.5555/563998.564020.
Citácia podľa MLA (8th ed.)Zalamea, Javier, et al. "Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures." Proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture, Jan. 2001, pp. 160-169, https://doi.org/10.5555/563998.564020.