Combining HW/SW mechanisms to improve NUMA performance of multi-GPU systems

Historically, improvement in GPU performance has been tightly coupled with transistor scaling. As Moore's Law slows down, performance of single GPUs may ultimately plateau. To continue GPU performance scaling, multiple GPUs can be connected using system-level interconnects. However, limited int...

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Veröffentlicht in:	2018 51st Annual IEEE ACM International Symposium on Microarchitecture (MICRO) S. 339 - 351
Hauptverfasser:	Young, Vinson, Jaleel, Aamer, Bolotin, Evgeny, Ebrahimi, Eiman, Nellans, David, Villa, Oreste
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	Piscataway, NJ, USA IEEE Press 20.10.2018 IEEE
Schriftenreihe:	ACM Conferences
Schlagworte:	Bandwidth Coherence Computer systems organization Computer systems organization > Dependable and fault-tolerant systems and networks DRAM-Cache General and reference General and reference > Cross-computing tools and techniques General and reference > Cross-computing tools and techniques > Performance GPU Graphics processing units Hardware Hardware > Integrated circuits Hardware > Integrated circuits > Semiconductor memory Hardware > Integrated circuits > Semiconductor memory > Dynamic memory HBM Memory Multi-GPU Networks Networks > Network performance evaluation NUMA Page-Migration Page-Replication Random access memory Social and professional topics Social and professional topics > Professional topics Social and professional topics > Professional topics > Computing profession Social and professional topics > Professional topics > Computing profession > Testing, certification and licensing Transistors page-migration HBM memory coherence page-replication Multi-GPU GPU DRAM-Cache NUMA
ISBN:	9781538662403, 153866240X
Online-Zugang:	Volltext
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