GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration
2.5D chiplet technology is gaining popularity for the efficiency of integrating multiple heterogeneous dies or chiplets on interposers, and it is also considered an ideal option for agile silicon system design by mitigating the huge design, verification, and manufacturing overhead of monolithic SoCs....
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| Vydané v: | 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) s. 1 - 9 |
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| Hlavní autori: | , , , , , , |
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| Jazyk: | English |
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ACM
29.10.2022
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| ISSN: | 1558-2434 |
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| Abstract | 2.5D chiplet technology is gaining popularity for the efficiency of integrating multiple heterogeneous dies or chiplets on interposers, and it is also considered an ideal option for agile silicon system design by mitigating the huge design, verification, and manufacturing overhead of monolithic SoCs. Although it significantly reduces development costs by chiplet reuse, the design and fabrication of interposers also introduce additional high non-recurring engineering (NRE) costs and development cycles which might be prohibitive for application-specific designs having low volume.To address this challenge, in this paper, we propose a reusable general interposer architecture (GIA) to amortize NRE costs and accelerate integration flows of interposers across different chiplet-based systems effectively. The proposed assembly-time configurable interposer architecture covers both active interposers and passive interposers considering diverse applications of 2.5D systems. The agile interposer integration is also facilitated by a novel end-to-end design automation framework to generate optimal system assembly configurations including the selection of chiplets, inter-chiplet network configuration, placement of chiplets, and mapping on GIA, which are specialized for the given target workload. The experimental results show that our proposed active GIA and passive GIA achieve 3.15x and 60.92x performance boost with 2.57x and 2.99x power saving over baselines respectively. |
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| AbstractList | 2.5D chiplet technology is gaining popularity for the efficiency of integrating multiple heterogeneous dies or chiplets on interposers, and it is also considered an ideal option for agile silicon system design by mitigating the huge design, verification, and manufacturing overhead of monolithic SoCs. Although it significantly reduces development costs by chiplet reuse, the design and fabrication of interposers also introduce additional high non-recurring engineering (NRE) costs and development cycles which might be prohibitive for application-specific designs having low volume.To address this challenge, in this paper, we propose a reusable general interposer architecture (GIA) to amortize NRE costs and accelerate integration flows of interposers across different chiplet-based systems effectively. The proposed assembly-time configurable interposer architecture covers both active interposers and passive interposers considering diverse applications of 2.5D systems. The agile interposer integration is also facilitated by a novel end-to-end design automation framework to generate optimal system assembly configurations including the selection of chiplets, inter-chiplet network configuration, placement of chiplets, and mapping on GIA, which are specialized for the given target workload. The experimental results show that our proposed active GIA and passive GIA achieve 3.15x and 60.92x performance boost with 2.57x and 2.99x power saving over baselines respectively. |
| Author | Li, Fuping Li, Xiaowei Wang, Yujie Wang, Ying Han, Yinhe Li, Huawei Cheng, Yuanqing |
| Author_xml | – sequence: 1 givenname: Fuping surname: Li fullname: Li, Fuping organization: Chinese Academy of Sciences,SKLP, Institute of Computing Technology – sequence: 2 givenname: Ying surname: Wang fullname: Wang, Ying organization: Chinese Academy of Sciences,SKLP, Institute of Computing Technology – sequence: 3 givenname: Yuanqing surname: Cheng fullname: Cheng, Yuanqing organization: Beihang University – sequence: 4 givenname: Yujie surname: Wang fullname: Wang, Yujie organization: Chinese Academy of Sciences,CICS, Institute of Computing Technology – sequence: 5 givenname: Yinhe surname: Han fullname: Han, Yinhe organization: Chinese Academy of Sciences,CICS, Institute of Computing Technology – sequence: 6 givenname: Huawei surname: Li fullname: Li, Huawei organization: Chinese Academy of Sciences,SKLP, Institute of Computing Technology – sequence: 7 givenname: Xiaowei surname: Li fullname: Li, Xiaowei organization: Chinese Academy of Sciences,SKLP, Institute of Computing Technology |
| BookMark | eNotj01LxDAYhKMouK49e_GQP9D1zVfTeivFrYUVQfS8JPXNbqS2Jc0e_PcG9TQw8zDMXJOLcRqRkFsGG8akuhcKSqH4RihZyUKekazSZQpAVJxpeU5WTKky51LIK5ItyycA8FIzrWFFntuufqA1fcXTYuyAtMURgxloN0YM87RgoHXojz5iH08BqZuScfCJbI5-HjD-kodgop_GG3LpzLBg9q9r8r59fGue8t1L2zX1LjdcljF3QghbOc7SDsc4gkFrARkUFSZVH1ybIr0xwG0BgjNelC4lyqJ2PXNiTe7-ej0i7ufgv0z43jNIBRUvxA_B7U9B |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO |
| DOI | 10.1145/3508352.3549464 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP) 1998-present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISBN | 9781450392174 1450392172 |
| EISSN | 1558-2434 |
| EndPage | 9 |
| ExternalDocumentID | 10069926 |
| Genre | orig-research |
| GrantInformation_xml | – fundername: National Natural Science Foundation of China funderid: 10.13039/501100001809 – fundername: Research and Development funderid: 10.13039/100006190 |
| GroupedDBID | 6IE 6IF 6IH 6IL 6IN AAWTH ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO FEDTE IEGSK IJVOP M43 OCL RIE RIL RIO |
| ID | FETCH-LOGICAL-a248t-f333b9f21028f12e0aebb0e1069eb0e5d27a6549a02b60321268feb05be7fc1f3 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 20 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000981574300041&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Aug 27 02:46:17 EDT 2025 |
| IsDoiOpenAccess | false |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-a248t-f333b9f21028f12e0aebb0e1069eb0e5d27a6549a02b60321268feb05be7fc1f3 |
| PageCount | 9 |
| ParticipantIDs | ieee_primary_10069926 |
| PublicationCentury | 2000 |
| PublicationDate | 2022-Oct.-29 |
| PublicationDateYYYYMMDD | 2022-10-29 |
| PublicationDate_xml | – month: 10 year: 2022 text: 2022-Oct.-29 day: 29 |
| PublicationDecade | 2020 |
| PublicationTitle | 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) |
| PublicationTitleAbbrev | ICCAD |
| PublicationYear | 2022 |
| Publisher | ACM |
| Publisher_xml | – name: ACM |
| SSID | ssj0002871770 ssj0020286 |
| Score | 2.3333185 |
| Snippet | 2.5D chiplet technology is gaining popularity for the efficiency of integrating multiple heterogeneous dies or chiplets on interposers, and it is also considered... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 1 |
| SubjectTerms | 2.5D integration chiplet interposer network-on-chip reusability |
| Title | GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration |
| URI | https://ieeexplore.ieee.org/document/10069926 |
| WOSCitedRecordID | wos000981574300041&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV09T8MwELVoxQALX0V8ywOrS2I7dswWVRSQoKoQSN0qOzkXlga1Kb-fcxJKFwaWJHIyJOeL793Z75mQawsyD_s-MkSrikmXJszmVjLrDEifOBM3OrNPejRKJxMzbsnqNRcGAOrFZ9APl_VcflHmq1Aqwz88UsZw1SEdrXVD1loXVAL018H52mwLG1Sr5RPL5EYkNdjoC0yIZNAX2NhMpY4lw71_vsU-6f2y8uh4HW8OyBbMD8nuhqDgEXm-f8xuaUZfYLUMnCjaqkrTZm1hif5Gs42pA4qQlWYzHBno4D2U3Kv6yVnjFj3yNrx7HTywdsMEZrlMK-aFEM74kMWlPuYQWXAuAsz6DOA5Kbi2Cr_fRtypSGDUUqnHO4kD7fPYi2PSnZdzOCFUFSq2OSZn1qO5sDMRtvgID8BlgaDglPSCZaafjSbG9McoZ3-0n5MdHogDOOpzc0G61WIFl2Q7_6o-louruie_AXawnLk |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV09T8MwED1BQQIWvor4xgNrSuI4TswWVZRWtFWFitStstNzYWlRm_L7OSehdGFgSSInQ3y-5N6d_Z4B7jWKzO376BFalZ4wSeTpTAtPG4XCRkYFpc5sN-73k9FIDSqyesGFQcRi8Rk23GUxlz-ZZytXKqMv3JdKcbkNO5EQPCjpWuuSigP_sXO_Kt-iBlmp-QQiegijAm40QkqJhFMY2NhOpYgmrcN_vscR1H95eWywjjjHsIWzEzjYkBQ8hd5zJ31kKXvF1dKxolilK83K1YVz8jiWbkweMAKtLJ3Sv4E1313RPS-enJaOUYe31tOw2faqLRM8zUWSezYMQ6Osy-MSG3D0NRrjI-V9CukcTXisJfVf-9xIP6S4JRNLdyKDsc0CG55BbTaf4TkwOZGBzig905bMRcNJwMX6dEAuJgQLLqDuLDP-LFUxxj9Gufyj_Q722sNed9zt9F-uYJ87GgHFAK6uoZYvVngDu9lX_rFc3Baj-g3QvqAA |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2022+IEEE%2FACM+International+Conference+On+Computer+Aided+Design+%28ICCAD%29&rft.atitle=GIA%3A+A+Reusable+General+Interposer+Architecture+for+Agile+Chiplet+Integration&rft.au=Li%2C+Fuping&rft.au=Wang%2C+Ying&rft.au=Cheng%2C+Yuanqing&rft.au=Wang%2C+Yujie&rft.date=2022-10-29&rft.pub=ACM&rft.eissn=1558-2434&rft.spage=1&rft.epage=9&rft_id=info:doi/10.1145%2F3508352.3549464&rft.externalDocID=10069926 |