How Good Is Your Verilog RTL Code? A Quick Answer from Machine Learning

Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or...

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Vydáno v:2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) s. 1 - 9
Hlavní autoři: Sengupta, Prianka, Tyagi, Aakash, Chen, Yiran, Hu, Jiang
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: ACM 29.10.2022
Témata:
Codes
Design automation
Encoding
Hardware design languages
Layout
Machine learning
Performance and Power
Prediction methods
Verilog RTL
ISSN:1558-2434
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Shrnutí:Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or even layout is completed. However, running synthesis merely as a feedback for HDL code is computationally not economical especially in early design phases when the code needs to be frequently modified. Furthermore, in late stages of design convergence burdened with high-impact engineering change orders (ECO's), design iterations become prohibitively expensive. To this end, we propose a machine learning approach to Verilog-based Register-Transfer Level (RTL) design assessment without going through the synthesis process. It would allow designers to quickly evaluate the performance-power tradeoff among different options of RTL designs. Experimental results show that our proposed technique achieves an average of 95% prediction accuracy in terms of post-placement analysis, and is 6 orders of magnitude faster than evaluation by running logic synthesis and placement.
ISSN:1558-2434
DOI:10.1145/3508352.3549375