How Good Is Your Verilog RTL Code? A Quick Answer from Machine Learning
Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or...
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| Vydáno v: | 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) s. 1 - 9 |
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| Jazyk: | angličtina |
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29.10.2022
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| ISSN: | 1558-2434 |
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| Abstract | Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or even layout is completed. However, running synthesis merely as a feedback for HDL code is computationally not economical especially in early design phases when the code needs to be frequently modified. Furthermore, in late stages of design convergence burdened with high-impact engineering change orders (ECO's), design iterations become prohibitively expensive. To this end, we propose a machine learning approach to Verilog-based Register-Transfer Level (RTL) design assessment without going through the synthesis process. It would allow designers to quickly evaluate the performance-power tradeoff among different options of RTL designs. Experimental results show that our proposed technique achieves an average of 95% prediction accuracy in terms of post-placement analysis, and is 6 orders of magnitude faster than evaluation by running logic synthesis and placement. |
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| AbstractList | Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or even layout is completed. However, running synthesis merely as a feedback for HDL code is computationally not economical especially in early design phases when the code needs to be frequently modified. Furthermore, in late stages of design convergence burdened with high-impact engineering change orders (ECO's), design iterations become prohibitively expensive. To this end, we propose a machine learning approach to Verilog-based Register-Transfer Level (RTL) design assessment without going through the synthesis process. It would allow designers to quickly evaluate the performance-power tradeoff among different options of RTL designs. Experimental results show that our proposed technique achieves an average of 95% prediction accuracy in terms of post-placement analysis, and is 6 orders of magnitude faster than evaluation by running logic synthesis and placement. |
| Author | Sengupta, Prianka Hu, Jiang Chen, Yiran Tyagi, Aakash |
| Author_xml | – sequence: 1 givenname: Prianka surname: Sengupta fullname: Sengupta, Prianka email: prianka.sengupta@tamu.edu organization: Texas A&M University,College Station,Texas,USA – sequence: 2 givenname: Aakash surname: Tyagi fullname: Tyagi, Aakash email: tyagi@cse.tamu.edu organization: Texas A&M University,College Station,Texas,USA – sequence: 3 givenname: Yiran surname: Chen fullname: Chen, Yiran email: yiran.chen@duke.edu organization: Duke University,Durham,N Carolina,USA – sequence: 4 givenname: Jiang surname: Hu fullname: Hu, Jiang email: jianghu@tamu.edu organization: Texas A&M University,College Station,Texas,USA |
| BookMark | eNotj0FLwzAYhqMoOGfPXjzkD3Qm-ZImPUkZrhtURJmCp5EmX2d1SyR1DP-9BT09h_fhheeSnIUYkJBrzmacS3ULihlQYgZKlqDVCclKbcaBQSm4lqdkwpUyuZAgL0g2DB-MMWE015pNSL2MR1rH6OlqoG_xkOgrpn4Xt_R53dB59HhHK_p06N0nrcJwxES7FPf0wbr3PiBt0KbQh-0VOe_sbsDsn1Pysrhfz5d581iv5lWTWyHNd94iByELB5Jxi6I1yvCO6xKEV15yXYjCSe3Rejta0gNYiaOpnBBOdS1Myc3fb4-Im6_U72362XDGinKMgl_MekvJ |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO |
| DOI | 10.1145/3508352.3549375 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE/IET Electronic Library (IEL) (UW System Shared) IEEE Proceedings Order Plans (POP) 1998-present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE/IET Electronic Library (IEL) (UW System Shared) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISBN | 9781450392174 1450392172 |
| EISSN | 1558-2434 |
| EndPage | 9 |
| ExternalDocumentID | 10069028 |
| Genre | orig-research |
| GrantInformation_xml | – fundername: Semiconductor Research Corporation funderid: 10.13039/100000028 – fundername: National Science Foundation funderid: 10.13039/100000001 |
| GroupedDBID | 6IE 6IF 6IH 6IL 6IN AAWTH ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO FEDTE IEGSK IJVOP M43 OCL RIE RIL RIO |
| ID | FETCH-LOGICAL-a248t-be13246c3401ae2b8581f17932d5d417626c47deada46c4d33a4e1ae5c22c5fb3 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 19 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000981574300088&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Aug 27 02:46:14 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-a248t-be13246c3401ae2b8581f17932d5d417626c47deada46c4d33a4e1ae5c22c5fb3 |
| PageCount | 9 |
| ParticipantIDs | ieee_primary_10069028 |
| PublicationCentury | 2000 |
| PublicationDate | 2022-Oct.-29 |
| PublicationDateYYYYMMDD | 2022-10-29 |
| PublicationDate_xml | – month: 10 year: 2022 text: 2022-Oct.-29 day: 29 |
| PublicationDecade | 2020 |
| PublicationTitle | 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) |
| PublicationTitleAbbrev | ICCAD |
| PublicationYear | 2022 |
| Publisher | ACM |
| Publisher_xml | – name: ACM |
| SSID | ssj0002871770 ssj0020286 |
| Score | 2.358303 |
| Snippet | Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 1 |
| SubjectTerms | Codes Design automation Encoding Hardware design languages Layout Machine learning Performance and Power Prediction methods Verilog RTL |
| Title | How Good Is Your Verilog RTL Code? A Quick Answer from Machine Learning |
| URI | https://ieeexplore.ieee.org/document/10069028 |
| WOSCitedRecordID | wos000981574300088&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LTwIxEG6EeNCLL4zv9OB1ke1jHydDiIAJEjRouJE-Zg0x2TULyN93Wlbk4sFbM22apu1MO-183xByq0KrjbWtQGbMBkJDGqjU6EAIyxLDTagzn7VkEA-HyWSSjiqwusfCAIAPPoOmK_q_fFuYpXsqQw13vLosqZFaHMdrsNbmQcVd_WO3-SpvCwVRxeUTCnnHpb9sNDk6RNxFFW4lU_FnSffgn6M4JI1fVB4dbc6bI7ID-THZ3yIUPCG9frGivaKw9HFOUZFL-oY1aN7oy3hAO4WFe9qmz8uZ-aDtfL6Ckjp8CX3yIZVAK7bV9wZ57T6MO_2gSpUQKCaSRaABvUoRGY7ukgKmE5mEmdM9ZqUVIVq8yIjY4rZR2EpYzpUAbCkNY0Zmmp-Sel7kcEaozFQiUsYA-xNppFWGfcc2S1tWM6nFOWm4OZl-rtkwpj_TcfGH_JLsMQcZQHvP0itSX5RLuCa75msxm5c3fg2_AWQQmtg |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LTwIxEG4UTdSLL4xve_C6yPaxj5MhRB5xIWjQcCN9zBJismsWkL9vW1bk4sFbM22apu1MO-183yB0L3wtldZ1j6dEe0xC7IlYSY8xTSJFlS9Tl7UkCfv9aDSKByVY3WFhAMAFn0HNFt1fvs7Vwj6VGQ23vLok2kY7nDHir-Ba6ycVe_kP7fYr_S0jCEo2H5_xB8rddaNGjUtEbVzhRjoVd5q0Dv85jiNU_cXl4cH6xDlGW5CdoIMNSsFT1O7kS9zOc427M2xUucDvpsYYOPw6THAz1_CIG_hlMVUfuJHNllBgizDBPRdUCbjkW51U0VvradjseGWyBE8QFs09CcavZIGixmESQGTEIz-12kc018w3Ni9QLNRm4wjTimlKBQPTkitCFE8lPUOVLM_gHGGeiojFhIDpj8WBFKnpO9RpXNeScMkuUNXOyfhzxYcx_pmOyz_kd2ivM-wl46Tbf75C-8QCCIz1J_E1qsyLBdygXfU1n86KW7ee36dcnh8 |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2022+IEEE%2FACM+International+Conference+On+Computer+Aided+Design+%28ICCAD%29&rft.atitle=How+Good+Is+Your+Verilog+RTL+Code%3F+A+Quick+Answer+from+Machine+Learning&rft.au=Sengupta%2C+Prianka&rft.au=Tyagi%2C+Aakash&rft.au=Chen%2C+Yiran&rft.au=Hu%2C+Jiang&rft.date=2022-10-29&rft.pub=ACM&rft.eissn=1558-2434&rft.spage=1&rft.epage=9&rft_id=info:doi/10.1145%2F3508352.3549375&rft.externalDocID=10069028 |