TransSizer: A Novel Transformer-Based Fast Gate Sizer

Gate sizing is a fundamental netlist optimization move and researchers have used supervised learning-based models in gate sizers. Recently, Reinforcement Learning (RL) has been tried for sizing gates (and other EDA optimization problems) but are very runtime-intensive. In this work, we explore a nov...

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Bibliographic Details
Published in:2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) pp. 1 - 9
Main Authors: Nath, Siddhartha, Pradipta, Geraldo, Hu, Corey, Yang, Tian, Khailany, Brucek, Ren, Haoxing
Format: Conference Proceeding
Language:English
Published: ACM 29.10.2022
Subjects:
Computational modeling
Computer architecture
Data models
generative model
Logic gates
Measurement
Netlist optimization
sizing
Training
Transformer
Transformers
ISSN:1558-2434
Online Access:Get full text
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Summary:Gate sizing is a fundamental netlist optimization move and researchers have used supervised learning-based models in gate sizers. Recently, Reinforcement Learning (RL) has been tried for sizing gates (and other EDA optimization problems) but are very runtime-intensive. In this work, we explore a novel Transformer-based gate sizer, TransSizer, to directly generate optimized gate sizes given a placed and unoptimized netlist. TransSizer is trained on datasets obtained from real tapeout-quality industrial designs in a foundry 5nm technology node. Our results indicate that TransSizer achieves 97% accuracy in predicting optimized gate sizes at the postroute optimization stage. Furthermore, TransSizer has a speedup of ∼1400X while delivering similar timing, power and area metrics when compared to a leading-edge commercial tool for sizing-only optimization.
ISSN:1558-2434
DOI:10.1145/3508352.3549442