Applying GNNs to Timing Estimation at RTL : (Invited Paper)

In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are performed only after physical synthesis. Encountered timing violations cause re-iterations of the design flow. Hence, timing estimations at initial design stages, such as Register Transfer Level (RTL), would...

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Vydáno v:2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) s. 1 - 8
Hlavní autoři: Lopera, Daniela Sanchez, Ecker, Wolfgang
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: ACM 29.10.2022
Témata:
Computer architecture
Delay
Delays
Design automation
Electronic Design Automation
Estimation
Graph Neural Networks
Measurement
Register Transfer Level
Slew
Timing Analysis
Topology
Training data
ISSN:1558-2434
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Shrnutí:In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are performed only after physical synthesis. Encountered timing violations cause re-iterations of the design flow. Hence, timing estimations at initial design stages, such as Register Transfer Level (RTL), would increase the quality of the results and lower the flow iterations. Machine learning has been used to estimate the timing behavior of chip components. However, existing solutions map EDA objects to Euclidean data without considering that EDA objects are represented naturally as graphs. Recent advances in Graph Neural Networks (GNNs) motivate the mapping from EDA objects to graphs for design metric prediction tasks at different stages. This paper maps RTL designs to directed, featured graphs with multidimensional node and edge features. These are the input to GNNs for estimating component delays and slews. An in-house hardware generation framework and open-source EDA tools for ASIC synthesis are employed for collecting training data. Experiments over unseen circuits show that GNN-based models are promising for timing estimation, even when the features come from early RTL implementations. Based on estimated delays, critical areas of the design can be detected, and proper RTL micro-architectures can be chosen without running long design iterations.
ISSN:1558-2434
DOI:10.1145/3508352.3561095