Applying GNNs to Timing Estimation at RTL : (Invited Paper)

In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are performed only after physical synthesis. Encountered timing violations cause re-iterations of the design flow. Hence, timing estimations at initial design stages, such as Register Transfer Level (RTL), would...

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Bibliographische Detailangaben

Veröffentlicht in:	2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) S. 1 - 8
Hauptverfasser:	Lopera, Daniela Sanchez, Ecker, Wolfgang
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	ACM 29.10.2022
Schlagworte:	Computer architecture Delay Delays Design automation Electronic Design Automation Estimation Graph Neural Networks Measurement Register Transfer Level Slew Timing Analysis Topology Training data
ISSN:	1558-2434
Online-Zugang:	Volltext
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