Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware

Distributed memory programming is the established paradigm used in high-performance computing (HPC) systems, requiring explicit communication between nodes and devices. When FPGAs are deployed in distributed settings, communication is typically handled either by going through the host machine, sacri...

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Vydáno v:SC19: International Conference for High Performance Computing, Networking, Storage and Analysis s. 1 - 33
Hlavní autoři: De Matteis, Tiziano, de Fine Licht, Johannes, Beranek, Jakub, Hoefler, Torsten
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: ACM 17.11.2019
Témata:
Computational modeling
Distributed Memory Programming
Field programmable gate arrays
Hardware
High performance computing
High-Level Synthesis Tools
Message passing
Performance evaluation
Programming
Reconfigurable computing
Routing
Semantics
Transient analysis
ISSN:2167-4337
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Shrnutí:Distributed memory programming is the established paradigm used in high-performance computing (HPC) systems, requiring explicit communication between nodes and devices. When FPGAs are deployed in distributed settings, communication is typically handled either by going through the host machine, sacrificing performance, or by streaming across fixed device-to-device connections, sacrificing flexibility. We present Streaming Message Interface (SMI), a communication model and API that unifies explicit message passing with a hardware-oriented programming model, facilitating minimal-overhead, flexible, and productive inter-FPGA communication. Instead of bulk transmission, messages are streamed across the network during computation, allowing communication to be seamlessly integrated into pipelined designs. We present a high-level synthesis implementation of SMI targeting a dedicated FPGA interconnect, exposing runtime-configurable routing with support for arbitrary network topologies, and implement a set of distributed memory benchmarks. Using SMI, programmers can implement distributed, scalable HPC programs on reconfigurable hardware, without deviating from best practices for hardware design.
ISSN:2167-4337
DOI:10.1145/3295500.3356201