Batch Sequential Black-box Optimization with Embedding Alignment Cells for Logic Synthesis

During the logic synthesis flow of EDA, a sequence of graph transformation operators are applied to the circuits so that the Quality of Results (QoR) of the circuits highly depends on the chosen operators and their specific parameters in the sequence, making the search space operator-dependent and i...

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Published in:2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) pp. 1 - 9
Main Authors: Feng, Chang, Lyu, Wenlong, Chen, Zhitang, Ye, Junjie, Yuan, Mingxuan, Hao, Jianye
Format: Conference Proceeding
Language:English
Published: ACM 29.10.2022
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ISSN:1558-2434
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Abstract During the logic synthesis flow of EDA, a sequence of graph transformation operators are applied to the circuits so that the Quality of Results (QoR) of the circuits highly depends on the chosen operators and their specific parameters in the sequence, making the search space operator-dependent and increasingly exponential. In this paper, we formulate the logic synthesis design space exploration as a conditional sequence optimization problem, where at each transformation step, an optimization operator is selected and its corresponding parameters are decided. To solve this problem, we propose a novel sequential black-box optimization approach without human intervention: 1) Due to the conditional and sequential structure of operator sequence with variable length, we build an embedding alignment cells based recurrent neural network as a surrogate model to estimate the QoR of the logic synthesis flow with historical data. 2) With the surrogate model, we construct acquisition function to balance exploration and exploitation with respect to each metric of the QoR. 3) We use multi-objective optimization algorithm to find the Pareto front of the acquisition functions, along which a batch of sequences, consisting of parameterized operators, are (randomly) selected to users for evaluation under the budget of computing resource. We repeat the above three steps until convergence or time limit. Experimental results on public EPFL benchmarks demonstrate the superiority of our approach over the expert-crafted optimization flows and other machine learning based methods. Compared to resyn2, we achieve 11.8% LUT-6 count descent improvements without sacrificing level values.
AbstractList During the logic synthesis flow of EDA, a sequence of graph transformation operators are applied to the circuits so that the Quality of Results (QoR) of the circuits highly depends on the chosen operators and their specific parameters in the sequence, making the search space operator-dependent and increasingly exponential. In this paper, we formulate the logic synthesis design space exploration as a conditional sequence optimization problem, where at each transformation step, an optimization operator is selected and its corresponding parameters are decided. To solve this problem, we propose a novel sequential black-box optimization approach without human intervention: 1) Due to the conditional and sequential structure of operator sequence with variable length, we build an embedding alignment cells based recurrent neural network as a surrogate model to estimate the QoR of the logic synthesis flow with historical data. 2) With the surrogate model, we construct acquisition function to balance exploration and exploitation with respect to each metric of the QoR. 3) We use multi-objective optimization algorithm to find the Pareto front of the acquisition functions, along which a batch of sequences, consisting of parameterized operators, are (randomly) selected to users for evaluation under the budget of computing resource. We repeat the above three steps until convergence or time limit. Experimental results on public EPFL benchmarks demonstrate the superiority of our approach over the expert-crafted optimization flows and other machine learning based methods. Compared to resyn2, we achieve 11.8% LUT-6 count descent improvements without sacrificing level values.
Author Feng, Chang
Chen, Zhitang
Hao, Jianye
Yuan, Mingxuan
Ye, Junjie
Lyu, Wenlong
Author_xml – sequence: 1
  givenname: Chang
  surname: Feng
  fullname: Feng, Chang
  email: fengchang1@huawei.com
  organization: Huawei Noah's Ark Lab,Shenzhen,China
– sequence: 2
  givenname: Wenlong
  surname: Lyu
  fullname: Lyu, Wenlong
  email: lvwenlong2@huawei.com
  organization: Huawei Noah's Ark Lab,Shenzhen,China
– sequence: 3
  givenname: Zhitang
  surname: Chen
  fullname: Chen, Zhitang
  email: chenzhitang2@huawei.com
  organization: Huawei Noah's Ark Lab,Hong Kong,China
– sequence: 4
  givenname: Junjie
  surname: Ye
  fullname: Ye, Junjie
  email: yejunjie4@huawei.com
  organization: Huawei Noah's Ark Lab,Shenzhen,China
– sequence: 5
  givenname: Mingxuan
  surname: Yuan
  fullname: Yuan, Mingxuan
  email: yuan.mingxuan@huawei.com
  organization: Huawei Noah's Ark Lab,Hong Kong,China
– sequence: 6
  givenname: Jianye
  surname: Hao
  fullname: Hao, Jianye
  email: haojianye@huawei.com
  organization: Huawei Noah's Ark Lab,Beijing,China
BookMark eNotjrFOwzAURQ0CiVI6szD4B1L8_OzYHtuqBaRKHQoLS-UmL60hcUpjBOXriQTD1RmuztW9ZhexjcTYLYgxgNL3qIVFLceolcMcz9jIGdsXAp0Eo87ZALS2mVSortio696EENIaMEYM2OvUp2LP1_TxSTEFX_Np7Yv3bNt-89UhhSb8-BTayL9C2vN5s6WyDHHHJ3XYxaZX-IzquuNVe-TLdhcKvj7FtKcudDfssvJ1R6N_DtnLYv48e8yWq4en2WSZealsyiQoQGEVWYWmgLyAPr60ZQ4kFDiyDhWW_eHSVd6gqeSWwOe5Jatt7w7Z3d9uIKLN4RgafzxtQIjcCanxF_hbU6Q
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1145/3508352.3549363
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE/IET Electronic Library
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISBN 9781450392174
1450392172
EISSN 1558-2434
EndPage 9
ExternalDocumentID 10069025
Genre orig-research
GroupedDBID 6IE
6IF
6IH
6IL
6IN
AAWTH
ABLEC
ADZIZ
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
CHZPO
FEDTE
IEGSK
IJVOP
M43
OCL
RIE
RIL
RIO
ID FETCH-LOGICAL-a248t-21413084e8437c16c116cad8d61e0419e89343d871d9fa737f2be1a668e858413
IEDL.DBID RIE
ISICitedReferencesCount 10
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000981574300055&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Aug 27 02:46:23 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a248t-21413084e8437c16c116cad8d61e0419e89343d871d9fa737f2be1a668e858413
PageCount 9
ParticipantIDs ieee_primary_10069025
PublicationCentury 2000
PublicationDate 2022-Oct.-29
PublicationDateYYYYMMDD 2022-10-29
PublicationDate_xml – month: 10
  year: 2022
  text: 2022-Oct.-29
  day: 29
PublicationDecade 2020
PublicationTitle 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
PublicationTitleAbbrev ICCAD
PublicationYear 2022
Publisher ACM
Publisher_xml – name: ACM
SSID ssj0002871770
ssj0020286
Score 2.2773628
Snippet During the logic synthesis flow of EDA, a sequence of graph transformation operators are applied to the circuits so that the Quality of Results (QoR) of the...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms Closed box
Computational modeling
Data models
Machine learning
Machine learning algorithms
Measurement
Recurrent neural networks
Title Batch Sequential Black-box Optimization with Embedding Alignment Cells for Logic Synthesis
URI https://ieeexplore.ieee.org/document/10069025
WOSCitedRecordID wos000981574300055&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NTwIxEG2UeNCLXxi_04PXItuWtntUAvGEJGhCvJBtO6sksBgWjP57p2VFLh48bNL0sGmm25nX2XlvCLlRDpRDj8h8DoJJUJalyguWauskwg2XNW1sNqF7PTMcpv2KrB65MAAQi8-gEYbxX76fuWVIleEJD7q6vLVNtrVWK7LWOqESoL8OH19128IJVWn5JLJ1K1oRbDQEXohEEP3caKYSY0l3_5-rOCD1X1Ye7a_jzSHZguKI7G0ICh6Tl3v0rG90EOuj8exOaEzQMTv7pI_oHKYV65KG9CvtTC348C56Nxm_xrIA2obJpKSIZGnowuzo4KtAiFiOyzp57nae2g-s6p7AMi7NgvEkxCcjwUihXYI7gk_mjVcJNGWSAiIVKTxazad5poXOuYUkU8qAQVSSiBNSK2YFnBLqEHZ5DZxDJmVulWn6IDxvg3qX9tackXow0-h9JZAx-rHQ-R_zF2SXBxYBhgCeXpLaYr6EK7LjPhbjcn4dt_UbqlOhuw
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LTwIxEG4UTdSLL4xve_C6yLbdbveoBIIRkQRMiBeybQclWcDwMPrvnZYVuXjwsEnTw6aZbme-zs73DSHX0oA06BED2wceCJA6SKTlQRJrIxBumLSsfbOJuNlU3W7SysnqngsDAL74DEpu6P_l27GZu1QZnnCnq8uidbIRCcHKC7rWMqXiwH_sPr_8voUTMlfzCUV0wyMPN0ocr0TcyX6utFPx0aS2-8917JHiLy-PtpYRZ5-sweiA7KxICh6Slzv0rW-07Suk8fRm1KfoAj3-pE_oHoY575K6BCytDjVY9y56mw1efWEArUCWTSliWer6MBva_hohSJwOpkXyXKt2KvUg758QpEyoWcBCF6GUACV4bELcE3xSq6wMoSzCBBCrCG7RajbppzGP-0xDmEqpQCEuCfkRKYzGIzgm1CDwsjEwBqkQfS1V2Trpee30u2Kr1QkpOjP13hcSGb0fC53-MX9Ftuqdx0avcd98OCPbzHEKMCCw5JwUZpM5XJBN8zEbTCeXfou_AUXZpQI
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2022+IEEE%2FACM+International+Conference+On+Computer+Aided+Design+%28ICCAD%29&rft.atitle=Batch+Sequential+Black-box+Optimization+with+Embedding+Alignment+Cells+for+Logic+Synthesis&rft.au=Feng%2C+Chang&rft.au=Lyu%2C+Wenlong&rft.au=Chen%2C+Zhitang&rft.au=Ye%2C+Junjie&rft.date=2022-10-29&rft.pub=ACM&rft.eissn=1558-2434&rft.spage=1&rft.epage=9&rft_id=info:doi/10.1145%2F3508352.3549363&rft.externalDocID=10069025