PRIMAL: Power Inference using Machine Learning

This paper introduces PRIMAL, a novel learning-based frame-work that enables fast and accurate power estimation for ASIC designs. PRIMAL trains machine learning (ML) models with design verification testbenches for characterizing the power of reusable circuit building blocks. The trained models can t...

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Bibliographic Details
Published in:Proceedings of the 56th Annual Design Automation Conference 2019 pp. 1 - 6
Main Authors: Zhou, Yuan, Ren, Haoxing, Zhang, Yanqing, Keller, Ben, Khailany, Brucek, Zhang, Zhiru
Format: Conference Proceeding
Language:English
Published: ACM 01.06.2019
Subjects:
Analytical models
Encoding
Estimation
Integrated circuit modeling
Logic gates
machine learning
Power estimation
Registers
Solid modeling
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Summary:This paper introduces PRIMAL, a novel learning-based frame-work that enables fast and accurate power estimation for ASIC designs. PRIMAL trains machine learning (ML) models with design verification testbenches for characterizing the power of reusable circuit building blocks. The trained models can then be used to generate detailed power profiles of the same blocks under different workloads. We evaluate the performance of several established ML models on this task, including ridge regression, gradient tree boosting, multi-layer perceptron, and convolutional neural network (CNN). For average power estimation, ML-based techniques can achieve an average error of less than 1% across a diverse set of realistic benchmarks, outperforming a commercial RTL power estimation tool in both accuracy and speed (15x faster). For cycle-by-cycle power estimation, PRIMAL is on average 50x faster than a commercial gate-level power analysis tool, with an average error less than 5%. In particular, our CNN-based method achieves a 35x speed-up and an error of 5.2% for cycle-by-cycle power estimation of a RISC-V processor core. Furthermore, our case study on a NoC router shows that PRIMAL can achieve a small estimation error of 4.5% using cycle-approximate traces from SystemC simulation.
DOI:10.1145/3316781.3317884