Power gating applied to MP-SoCs for standby-mode power management

Complex SoCs from servers to intelligent sensors are increasingly built up from heterogeneous IP cores and subsystems. Accelerator blocks or additional processor cores support both general purpose and graphics optimized processing in mobile SoCs, but the number of cores that may be simultaneously ac...

Celý popis

Uloženo v:

Podrobná bibliografie
Vydáno v:	2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) s. 1 - 5
Hlavní autor:	Flynn, David
Médium:	Konferenční příspěvek
Jazyk:	angličtina
Vydáno:	New York, NY, USA ACM 29.05.2013 IEEE
Edice:	ACM Conferences
Témata:	Central Processor Unit (CPU) Clocks Computer systems organization > Embedded and cyber-physical systems Computer systems organization > Real-time systems Dynamic Voltage and Frequency Scaling (DVFS) Electronic Design Automation (EDA) energy-efficiency Hardware > Electronic design automation > High-level and register-transfer level synthesis Hardware > Emerging technologies Hardware > Integrated circuits > Logic circuits > Sequential circuits Hardware > Very large scale integration design Implementation IP (IIP) Intellectual Property (IP) IP-deployment Latches Logic gates Logical IP (LIP) low-power Multi-Threshold CMOS (MTCMOS) Multi-Voltage (MV) Physical IP (PIP) power intent Power-Gating (PG) Rails Registers standard-cell State-Retention (SR) System-on-chip System-on-Chip (SoC) standard-cell physical IP (PIP) low-power implementation IP (IIP) power-gating (PG) IP-deployment dynamic voltage and frequency scaling (DVFS) multi-voltage (MV) intellectual property (IP) system-on-chip (SoC) multi-threshold CMOS (MTCMOS) electronic design automation (EDA) power intent central processor unit (CPU) logical IP (LIP) energy-efficiency state-retention (SR)
ISBN:	1450320716, 9781450320719
ISSN:	0738-100X
On-line přístup:	Získat plný text
Tagy:	Přidat tag Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!

Buďte první, kdo okomentuje tento záznam!