Efficient Hardware Acceleration of CNNs using Logarithmic Data Representation with Arbitrary log-base

Efficient acceleration of Deep Neural Networks is a manifold task. In order to save memory requirements and reduce energy consumption we propose the use of dedicated accelerators with novel arithmetic processing elements which use bit shifts instead of multipliers. While a regular power-of-2 quantiz...

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Vydáno v:2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) s. 1 - 8
Hlavní autoři: Vogel, Sebastian, Liang, Mengyu, Guntoro, Andre, Stechele, Walter, Ascheid, Gerd
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: ACM 01.11.2018
Témata:
Convolution
Hardware
Mathematical model
Memory management
Neural networks
Quantization (signal)
Task analysis
ISSN:1558-2434
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Shrnutí:Efficient acceleration of Deep Neural Networks is a manifold task. In order to save memory requirements and reduce energy consumption we propose the use of dedicated accelerators with novel arithmetic processing elements which use bit shifts instead of multipliers. While a regular power-of-2 quantization scheme allows for multiplierless computation of multiply-accumulate-operations, it suffers from high accuracy losses in neural networks. Therefore, we evaluate the use of powers-of-arbitrary-log-bases and confirmed their suitability for quantization of pre-trained neural networks. The presented method works without retraining of the neural network and therefore is suitable for applications in which no labeled training data is available. In order to verify our proposed method, we implement the log-based processing elements into a neural network accelerator on an FPGA. The hardware efficiency is evaluated in terms of FPGA utilization and energy requirements in comparison to regular 8-bit-fixed-point multiplier based acceleration. Using this approach hardware resources are minimized and power consumption is reduced by 22.3%.
ISSN:1558-2434
DOI:10.1145/3240765.3240803