Load value prediction via path-based address prediction avoiding mispredictions due to conflicting stores

Current flagship processors excel at extracting instruction-level-parallelism (ILP) by forming large instruction windows. Even then, extracting ILP is inherently limited by true data dependencies. Value prediction was proposed to address this limitation. Many challenges face value prediction, in thi...

Full description

Saved in:

Bibliographic Details
Published in:	MICRO-50 : the 50th annual IEEE/ACM International Symposium on Microarchitecture : proceedings : October 14-18, 2017, Cambridge, MA pp. 423 - 435
Main Authors:	Sheikh, Rami, Cain, Harold W., Damodaran, Raguram
Format:	Conference Proceeding
Language:	English
Published:	New York, NY, USA ACM 14.10.2017
Series:	ACM Conferences
Subjects:	Address Prediction Computer systems organization > Architectures > Serial architectures > Pipeline computing Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing Computer systems organization > Architectures > Serial architectures > Superscalar architectures History Machinery Microarchitecture Path-based Predictor Pipelines Prefetching Registers Value Prediction value prediction address prediction path-based predictor microarchitecture
ISBN:	1450349528, 9781450349529
ISSN:	2379-3155
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Be the first to leave a comment!