Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures

This paper proposes an efficient algorithm to synthesize prefix graph structures that yield adders with the best performance-area trade-off. For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of pr...

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Bibliographic Details
Published in:2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 8
Main Authors: Roy, Subhendu, Choudhury, Mihir, Puri, Ruchir, Pan, David Z.
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 29.05.2013
IEEE
Series:ACM Conferences
Subjects:
Adders
Algorithm design and analysis
Bottom-up approach
Data structures
Dynamic programming
Hardware > Integrated circuits > Logic circuits
Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits
Heuristic algorithms
Indexes
Logic synthesis
Parallel prefix adder
Runtime
logic synthesis
parallel prefix adder
bottom-up approach
ISBN:1450320716, 9781450320719
ISSN:0738-100X
Online Access:Get full text
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Summary:This paper proposes an efficient algorithm to synthesize prefix graph structures that yield adders with the best performance-area trade-off. For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of prefix graph subject to constraints like bit-wise output logic level. Besides having the best performance-area trade-off our approach, unlike existing techniques, can (i) handle more complex constraints such as maximum node fanout or wire-length that impact the performance/area of a design and (ii) generate several feasible solutions that minimize the objective function. Generating several optimal solutions provides the option to choose adder designs that mitigate constraints such as wire congestion or power consumption that are difficult to model as constraints during logic synthesis. Experimental results demonstrate that our approach improves performance by 3% and area by 9% over even a 64-bit full custom designed adder implemented in an industrial high-performance design.
ISBN:1450320716
9781450320719
ISSN:0738-100X
DOI:10.1145/2463209.2488793