Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures

This paper proposes an efficient algorithm to synthesize prefix graph structures that yield adders with the best performance-area trade-off. For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of pr...

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Veröffentlicht in:	2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) S. 1 - 8
Hauptverfasser:	Roy, Subhendu, Choudhury, Mihir, Puri, Ruchir, Pan, David Z.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	New York, NY, USA ACM 29.05.2013 IEEE
Schriftenreihe:	ACM Conferences
Schlagworte:	Adders Algorithm design and analysis Bottom-up approach Data structures Dynamic programming Hardware > Integrated circuits > Logic circuits Hardware > Integrated circuits > Logic circuits > Arithmetic and datapath circuits Heuristic algorithms Indexes Logic synthesis Parallel prefix adder Runtime logic synthesis parallel prefix adder bottom-up approach
ISBN:	1450320716, 9781450320719
ISSN:	0738-100X
Online-Zugang:	Volltext
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