ToPoliNano nanoarchitectures design made real
Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, ap...
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| Published in: | 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) pp. 160 - 167 |
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| Main Authors: | , , , , , |
| Format: | Conference Proceeding |
| Language: | English |
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New York, NY, USA
ACM
04.07.2012
IEEE |
| Series: | ACM Conferences |
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| ISBN: | 1450316719, 9781450316712 |
| ISSN: | 2327-8218 |
| Online Access: | Get full text |
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| Abstract | Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing.
We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits.
ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologies. |
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| AbstractList | Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing.
We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits.
ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologies. Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing. We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits. ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologies. |
| Author | Graziano, M. Riente, F. Chiabrando, D. Zamboni, M. Frache, S. Turvani, G. |
| Author_xml | – sequence: 1 givenname: S. surname: Frache fullname: Frache, S. email: stefano.frache@polito.it organization: Politecnico di Torino, Torino, Italy – sequence: 2 givenname: D. surname: Chiabrando fullname: Chiabrando, D. organization: Politecnico di Torino, Torino, Italy – sequence: 3 givenname: M. surname: Graziano fullname: Graziano, M. email: mariagrazia.graziano@polito.it organization: Politecnico di Torino, Torino, Italy – sequence: 4 givenname: F. surname: Riente fullname: Riente, F. organization: Politecnico di Torino, Torino, Italy – sequence: 5 givenname: G. surname: Turvani fullname: Turvani, G. organization: Politecnico di Torino, Torino, Italy – sequence: 6 givenname: M. surname: Zamboni fullname: Zamboni, M. email: maurizio.zamboni@polito.it organization: Politecnico di Torino, Torino, Italy |
| BookMark | eNqNj81Kw0AUhQesYFO7duELuEm8d2bu_Cyl-AdFXdT1cCfOQLTNSOLGtzeleQBXB87hO_BVYtGXPglxhdAgarqV1pD22ByTJJyJampBobHoF2IplbS1k-guxHocPwEADSF4WopqV97KvnvhvlyK88z7Ma3nXIn3h_vd5qnevj4-b-62NUttf2pmi661H6gUaY2xxRiRjc85ObI5RyBSLgK3DJEiREVMYBLabKLKXq3E9em3SymF76E78PAbjDYayU1rc1q5PYRYytcYEMLRMsyWYbYMcehSnoCbfwLqD6a2T1s |
| ContentType | Conference Proceeding |
| Copyright | 2012 ACM |
| Copyright_xml | – notice: 2012 ACM |
| DBID | 6IE 6IL CBEJK RIE RIL |
| DOI | 10.1145/2765491.2765520 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Xplore POP ALL IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP All) 1998-Present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EndPage | 167 |
| ExternalDocumentID | 6464158 |
| Genre | orig-research |
| GroupedDBID | 6IE 6IF 6IK 6IL 6IN AAJGR ACM ADPZR ALMA_UNASSIGNED_HOLDINGS APO BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK GUFHI IEGSK IERZE OCL RIB RIC RIE RIL 6IH AAWTH ACGFS ADZIZ CHZPO IPLJI |
| ID | FETCH-LOGICAL-a247t-aa718c7d1335441bc1bb1a69ffe857ffb05538b0aca0b5b0b35a506e17f6b3f93 |
| IEDL.DBID | RIE |
| ISBN | 1450316719 9781450316712 |
| ISICitedReferencesCount | 15 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000328120600023&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 2327-8218 |
| IngestDate | Wed Aug 27 04:22:39 EDT 2025 Wed Jan 31 06:38:29 EST 2024 |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
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| LinkModel | DirectLink |
| MeetingName | NANOARCH '12: IEEE/ACM International Symposium on Nanoscale Architectures |
| MergedId | FETCHMERGED-LOGICAL-a247t-aa718c7d1335441bc1bb1a69ffe857ffb05538b0aca0b5b0b35a506e17f6b3f93 |
| PageCount | 8 |
| ParticipantIDs | acm_books_10_1145_2765491_2765520 ieee_primary_6464158 acm_books_10_1145_2765491_2765520_brief |
| PublicationCentury | 2000 |
| PublicationDate | 20120704 2012-July |
| PublicationDateYYYYMMDD | 2012-07-04 2012-07-01 |
| PublicationDate_xml | – month: 07 year: 2012 text: 20120704 day: 04 |
| PublicationDecade | 2010 |
| PublicationPlace | New York, NY, USA |
| PublicationPlace_xml | – name: New York, NY, USA |
| PublicationSeriesTitle | ACM Conferences |
| PublicationTitle | 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) |
| PublicationTitleAbbrev | NanoArch |
| PublicationYear | 2012 |
| Publisher | ACM IEEE |
| Publisher_xml | – name: ACM – name: IEEE |
| SSID | ssj0001651095 ssj0002001145 |
| Score | 1.5781673 |
| Snippet | Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or... |
| SourceID | ieee acm |
| SourceType | Publisher |
| StartPage | 160 |
| SubjectTerms | Applied computing -- Physical sciences and engineering -- Electronics Computer architecture Fabrics Hardware -- Electronic design automation -- Physical design (EDA) Hardware -- Emerging technologies Hardware -- Very large scale integration design Integrated circuit modeling Layout Nanoscale devices Routing Tiles |
| Subtitle | nanoarchitectures design made real |
| Title | ToPoliNano |
| URI | https://ieeexplore.ieee.org/document/6464158 |
| WOSCitedRecordID | wos000328120600023&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1JSwMxFH60xYNeXFqxbowgeHHazLRZxqtYPJUeKvQ2ZIWK7UgXf78vabQVBPEySxiG8BLekve-9wHcOucyybRJReEhOarIUskykWqWG8Gkc5abQDbBh0MxmRSjGtx_Y2GstaH4zHb8Y8jlm0qv_VFZl_UZ2htRhzrnfIPV2p6nMNxdEWP6GhJs3tWngVsuR0WMpizguijx2O-s-Gr3FN_z2PYHB7o5Zxg1YfCId-qJwOtSz36wrwTjMzj837SPoLVF8SWjb_t0DDU7P4GDnQaETeiMK18Ahyq2ekj8dTevsExMKO9IZtLYBJ3Ltxa8DJ7Gj89pZFBIZd7nq1RKND2aGwxEPdeY0plSuDQFLoGg3DlFKCo8RaSWRFFFVI9KSpjNuGOq54reKTTm1dyeQWKF9TTF3BlK-qZg-C9uUOrWmAw1qmjDDUqp9KHBstygnWkZJVlGSbbh7s9vSrWYWteGppdj-b5puVFGEZ7_PnwB--jHxCraS2isFmt7BXv6YzVdLq7DPvkEeCWwhQ |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1bS8MwFD5sU1BfvGzivFYQfLFb2zVJ66s4Js6xhwl7C0mTwMStsou_35OsbhME8aWXUEo4CeeSc77zAdwYY0JBM-UnqYXkyDT0BQ0TP6ORSqgwRjPlyCZYr5cMh2m_BHcrLIzW2hWf6YZ9dLl8lWcLe1TWpDFFe5OUYYvEcRQu0VrrExWK-6tAmb65FJt19oljl4tQFaMxc8guElj0d5h-N3wq3qOi8Q8ONCNGMW7C8BHvxFKBl0U2_sG_4sxPe_9_Ez-A2hrH5_VXFuoQSnpyBHsbLQir0BjktgQOlWx-79nrZmZh5ilX4OGNhdIeupfvNXhtPw4eOn7BoeCLKGZzXwg0PhlTGIpatjGZhVLi4qS4CAlhxsiAoMqTgchEIIkMZIsIElAdMkNly6StY6hM8ok-AU8n2hIVM6NIEKuU4r-YQqlrpULUqUkdrlFK3AYHM77EOxNeSJIXkqzD7Z_fcDkdaVOHqpUj_1g23eCFCE9_H76Cnc7gpcu7T73nM9hFr6aoqT2Hyny60BewnX3OR7PppdszX-L6s8w |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2012+IEEE%2FACM+International+Symposium+on+Nanoscale+Architectures+%28NANOARCH%29&rft.atitle=ToPoliNano%3A+Nanoarchitectures+design+made+real&rft.au=Frache%2C+S.&rft.au=Chiabrando%2C+D.&rft.au=Graziano%2C+M.&rft.au=Riente%2C+F.&rft.date=2012-07-01&rft.pub=IEEE&rft.isbn=9781450316712&rft.issn=2327-8218&rft.spage=160&rft.epage=167&rft_id=info:doi/10.1145%2F2765491.2765520&rft.externalDocID=6464158 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=2327-8218&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=2327-8218&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=2327-8218&client=summon |

